Evaluation of Energy Efficient High Performance Power Gated Programmable Logic Array’s Under 65 nm Process Technology

Abstract

The Programmable Logic Array (PLA) forms the major building block in the implementation of sequential and combinational functionalities in VLSI based embedded systems. Increased sub threshold leakage current resulting from the scaling down of the microprocessors carrying PLA causes high power dissipation. In order to improve the energy consumption of future electronic products, we propose a power gating method involving sleepy modes at transistor level implemented using 65 nm technology. This paper describes the design and analysis of PLA’s with footer switches for power gating. A comparative analysis has been made between the AND array, OR array and the inverter elements of the proposed PLA’s and the conventional one. Results produced through simulation confirms an optimized power reduction and the transient analysis of the proposed PLA models is proved to be much better than the conventional PLA.