A built-in self-test PLA design with full fault coverage

Abstract

A built-in self-test (BIST) PLA (programmable logic array) design using a new technique for on-chip storage and retrieval of the compressed signature of a fault-free PLA is proposed. The design uses function-independent test input sequences, and provides function-independent test responses. Additional features of the proposed BIST PLA design are: (1) simplified implementation of test evaluator, (2) reduced test length (2n/sub i/n/sub p/ test inputs for a PLA with n/sub i/ inputs and n/sub p/ product lines), (3) full fault coverage in the naked PLA, (4) crosspoint fault locatability, and (5) only three extra pinouts. The proposed input decoder augmentation will not result in any performance degradation. With these features, the proposed design is more efficient than other BIST PLA designs reported in the literature. >