On yield consideration for the design of redundant programmable logic arrays

Abstract

This paper presents the design of a programmable logic array with redundancy. The design allows for the repair of a defective chip by including the redundancy circuits to a conventional PLA. When the redundancy technique is implemented into the VLSI or WSI chip design, the increased cost is proportional to the increased chip silicon area. Indeed, the additional spare lines may increase the silicon area and propagation delay. However, if the provided redundancy can be efficiently utilized to repair the defective chip, then the additional spare lines may increase rather decrease the chip yields. The objective of the present paper is to analyze the possibility of yield enhancement rhrough redundant design.