A design of programmable logic arrays with random pattern-testability

Abstract

A testable design of programmable logic arrays (PLAs) with high fault coverage for random test patterns is introduced. Low area overhead is achieved by adding a mask array between the input-decoder and the AND array of the PLA. Several variations of the proposed approach are presented. The probability of fault detection and the test length are examined for both stuck-type and crosspoint-type faults to estimate the fault coverage achievable with the random patterns. >