Abstract
An automated Programmable Logic Array (PLA) design system that is fully compatible with the density and power constraints of VLSI is described. A low power CMOS version of the PLA has been integrated into a technology independent, automated PLA generation system to provide a self-contained, highly functional and low power, dense cell design capability. A description of the Complementary Programmable Logic Array (CPLA) technique is provided, particularly in terms of its integration into the automated PLA design system. Details of the system's input formats, minimization and verification capabilities, design flexibility, CAD compatibility, and processing speeds are discussed.
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