Power Consumption Overhead Research Articles

9.1 µW keyword spotting processor based on optimized MFCC and small‐footprint TENet in 28‐nm CMOS

AbstractThis letter proposes a low‐power keyword spotting (KWS) architecture based on a modified temporal efficient neural network (TENet) and a simplified mel‐frequency cepstrum coefficient (MFCC) algorithm. The optimized MFCC algorithm reduces the computational load by 82% for multiplications and 66% for additions. An efficient hardware architecture and data flow for TENet have been designed, resulting in a 3.1× reduction in the operating cycle compared to similar work. The parameter count and computational load are reduced by 3.7× and 2.8×, respectively, and the accuracy reaches 95.36% for ten keywords in the Google Speech Command Dataset (GSCD). Operating at a frequency of 16 KHz for MFCC and 100 KHz for NN accelerator on a 28 nm process, the power consumption overhead is 9.1 µW.

Design of soft error correction flip-flop cells for highly reliable applications

With the development of technology, the vulnerability of integrated circuits to Single Event Effect (SEE) increases, and the sensitivity of flip-flops to soft errors induced by Single Event Transient (SET) and Single Event Upset (SEU) increases. Fault tolerant design is necessary for high reliability applications. In this work, a Soft Error Correction Flip-Flop 1(SEC FF1) is proposed, which can correct soft errors induced by SET and SEU at low clock phase without additional clock cycle. It has the lowest area and power consumption overhead and the lowest Power-Delay Product (PDP) compared with other radiation hardened flip-flops. In order to correct soft errors earlier, a variant of SEC FF1, SECFF2, is proposed at the cost of power consumption and switching delay. As the feature size of transistors shrinks, Double Node Upset (DNU) induced by single-event charge sharing is becoming an emerging reliability challenge. In order tolerate DNU, variant of SEC FFs, DNU Correction (DNUC) FFs, are proposed. In addition, the delay element used in the radiation-hardened flip-flops is also introduced.

A 10-Bit 400 MS/s Dual-Channel Time-Interleaved SAR ADC Based on Comparator Multiplexing

This paper proposes a 10-bit 400 MS/s dual-channel time-interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC) immune to offset mismatch between channels. A novel comparator multiplexing structure is proposed in our design to mitigate comparator offset mismatch between channels and improve ADC dynamic performance. Compared to traditional TI-SAR ADC utilizing offset calibration technique, hardware and power consumption overhead are minimized in our design. In addition, a split capacitive digital-to-analog converter (CDAC) and a double-tail dynamic comparator using the clock decoupling technique were applied to eliminate comparator common mode input voltage shift, ensuring conversion accuracy and boosting speed. A 400 MS/s 10-bit dual-channel TI-SAR ADC with comparator multiplexing was designed in 40 nm CMOS and compared to the conventional one. The simulated ADC ENOB and SFDR with 6σ offset mismatch were improved from 5.0-bit and 32.2 dB to 9.7-bit and 77.2 dB, respectively, confirming the merits of the proposed design compared to current state-of-the-art works.

Efficient Protection of FPGA Implemented LDPC Decoders Against Single Event Upsets (SEUs) on Configuration Memories

Low Density Parity Check (LDPC) codes are used in 5G systems for traffic channels due to their excellent error correction capability for long sequences, and the Min-Sum algorithm is widely applied in practical implementations of LDPC decoders due to its low complexity. If the decoder is implemented on a SRAM-based field-programmable gate array (SRAM-FPGA), the radiation-induced single-event upsets (SEUs) can affect the operation of the LDPC decoder by corrupting the configuration memory, which can change the circuit functionality and will not be corrected unless the FPGA is reconfigured. Therefore, protection of LDPC decoders with low overhead is an important problem, especially for resource-limited on-board space systems. In this paper, an efficient Duplicate With Comparison (DWC) protection scheme is proposed based on the different distribution of the parity check sum of the LDPC decoder in the error-free case and the faulty case. In particular, the check sum accumulation number and threshold are optimized to achieve high detection probability with short delay. FPGA based implementation and hardware fault injection experiments are conducted to evaluate the performance of the proposed schemes. Experimental results show that, the effect of SEUs on the LDPC decoder can be completely eliminated by the proposed scheme with 2 times computational overhead and 1.69 times power consumption overhead compared to the unprotected decoder.

On-Chip Fast Signal Generation and Low-Power SAR ADC for SiPM Readout

This article presents an ON-chip fast signal generator and a successive-approximation-register (SAR) analog-to-digital data converter (ADC) for silicon photomultiplier (SiPM) readout applications. The high-pass filter (HPF)-based fast-signal generator sharpens the rising edge of the standard SiPM output signal reducing time jitter due to the dark counts of the detector. It is implemented by leveraging the equivalent resistance of the current mirror transistor and the ac-coupling capacitor between the current mirror and the current discriminator to avoid hardware and power consumption overhead. Compared with OFF-chip solutions, the ON-chip approach eliminates the packaging pins and high-speed buffers needed for carrying the fast signals reducing packaging complexity and power consumption of the readout system. The energy quantizer utilizes the SiPM charge integrator as the ADC track-and-hold (T/H) circuit to improve the front-end power efficiency. The fast signal generator and the SAR ADC are implemented in a current-mode application-specific integrated circuit (ASIC) designed in a 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS technology. Measurement results show that the ON-chip fast signal generator is effective in improving the timing performance of the readout system. The timing resolutions are measured using SensL’s <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3\times $ </tex-math></inline-formula> 3 mm2 SiPM device with a terminal capacitance of 850 pF using an ultrashort laser pulser. Measurement results show that the fast signal generator improves the timing resolution by 23.4% compared with timing measurement using the standard output signal when the output charge is 300 pC. The ASIC achieved a measured ADC signal-to-noise-distortion ratio (SNDR) of 53.08 dB and a spurious-free dynamic range (SFDR) of 62.74 dB at 1 MS/s and a maximum front-end gain nonlinearity of 3.3% over 20–800-pC input charge range while dissipating 4.1 mW of power from a 1.8-V supply.

Low Area and Low Power Threshold Implementation Design Technique for AES S-Box

Threshold implementation (TI) is a promising countermeasure against side-channel attacks (SCA) in the presence of glitches. However, the hardware implementation of TI in S-box needs a large number of D flip-flops to synchronize intermediate signals, which results in a large silicon area and power consumption overhead. In this brief, we present the low area and low power TI design technique for advanced encryption standard (AES) S-box. In the proposed approach, instead of using D flip-flops, low-cost synchronization circuits such as customized tri-state XOR gates, tri-state buffers, and D latches are efficiently adopted with critical path replica (CPR) circuits. As a result, the proposed TI S-box implementation with 28nm CMOS process shows up to 33.7% area and 44.3% power savings. The security of the proposed TI AES S-box against side-channel attacks is also verified with test vector leakage assessment (TVLA) tests.

A Configurable Spiking Convolution Architecture Supporting Multiple Coding Schemes on FPGA

In this brief, an event-driven spiking convolution architecture with multi-kernel and multi-layer capability is designed. The proposed architecture can be configured in multiple-spike (MS) mode or single-spike (SS) mode to adapt to different spiking convolution neural network (SCNN) models with either rate coding scheme or temporal coding scheme. A skipped zero kernel step is designed to reduce access neuron membrane potentials in memories. In addition, the proposed design supports two pooling methods for increasing flexibility. The proposed architecture is implemented in a Xilinx Kintex-7 FPGA development board, and two SCNN models with different coding schemes are applied to verify the efficiency of the architecture. For the first SCNN model with rate coding scheme, the proposed architecture achieves a 99% classification accuracy with 0.46 mJ/classification. For the second SCNN model with temporal coding scheme, the proposed architecture obtains a classification accuracy over 95.4% with 7.4 uJ/classification. Experimental results demonstrate that the proposed design is adaptable and has a low power consumption overhead.

Learning on the Rings

This paper presents ssLOTR (self-supervised learning on the rings), a system that shows the feasibility of designing self-supervised learning based techniques for 3D finger motion tracking using a custom-designed wearable inertial measurement unit (IMU) sensor with a minimal overhead of labeled training data. Ubiquitous finger motion tracking enables a number of applications in augmented and virtual reality, sign language recognition, rehabilitation healthcare, sports analytics, etc. However, unlike vision, there are no large-scale training datasets for developing robust machine learning (ML) models on wearable devices. ssLOTR designs ML models based on data augmentation and self-supervised learning to first extract efficient representations from raw IMU data without the need for any training labels. The extracted representations are further trained with small-scale labeled training data. In comparison to fully supervised learning, we show that only 15% of labeled training data is sufficient with self-supervised learning to achieve similar accuracy. Our sensor device is designed using a two-layer printed circuit board (PCB) to minimize the footprint and uses a combination of Polylactic acid (PLA) and Thermoplastic polyurethane (TPU) as housing materials for sturdiness and flexibility. It incorporates a system-on-chip (SoC) microcontroller with integrated WiFi/Bluetooth Low Energy (BLE) modules for real-time wireless communication, portability, and ubiquity. In contrast to gloves, our device is worn like rings on fingers, and therefore, does not impede dexterous finger motion. Extensive evaluation with 12 users depicts a 3D joint angle tracking accuracy of 9.07° (joint position accuracy of 6.55mm) with robustness to natural variation in sensor positions, wrist motion, etc, with low overhead in latency and power consumption on embedded platforms.

Low-overhead inverted LUT design for bounded DNN activation functions on floating-point vector ALUs

An inference engine uses floating-point numbers to provide high accuracy in deep neural network computing despite its computing resource limitations. However, the computation for non-linear activation functions occurs the performance bottleneck, and we may alleviate it by adopting a lookup table (LUT) method. However, the floating-point number system’s characteristic, where intervals between mantissa numbers differ depending on their exponent values, makes it challenging to calculate LUT index values and produce the error-tolerant outputs.This paper proposes a floating-point-based lookup table (FP-LUT) that produces minimal errors and requires negligible hardware cost, especially for vector arithmetic logic units (ALUs), using bfloat16 recently proposed for both inference and training processes. Instead of calculating the index using the function input value, we apply the principle of an inverse function for our design, especially targeting bounded DNN activation functions. We divide a range of function output values linearly by the number of LUT entry sizes and store the corresponding input values in the LUT. Then, we compare the incoming input value with the stored LUT values, find the corresponding address, and convert it into an FP format for the output. We applied our 32-entry FP-LUT to the in-house 8-way bfloat16 MAC unit to support four DNN activation functions: logistic sigmoid, hyper-tangent, soft sign, and ISRU, which incurs only 1.22% and 0.46% of the area and power consumption overhead. Our accuracy analysis shows that with only an entry size of 1/8 compared to state-of-the-art 16-bit fixed-point LUT methods and the small logic overhead, FP-LUT reduces the average errors by 51.8%, 28.4%, 14.4%, and 26.1% in those functions on our test datasets, respectively. Additionally, we show that our scheme satisfies all application-defined accuracy.

Optimizing the placement of cloud data center in virtualized environment

&lt;p&gt;&lt;span&gt;In cloud mobile networks, precise assessment for the position of the virtualization powered cloud center would improve the capacity limit, latency and energy efficiency (EEf). This paper utilized the Monte Carlo oriented particle swarm optimization (PSO) and genetic algorithm (GA) to first, obtain the optimal number of virtual machines (VMs) that maximize the EEf of the mobile cloud center, second, optimize the position of the mobile data center. To fulfil such examination, a power evaluation framework is proposed to shape the power utilization of a virtualized server while hosting an amount of VMs. In addition, the total power consumption of the network is examined, including data center and radio units (RUs). This evaluation is based on linear modelling of the network parameters, such as resource blocks, number of VMs, transmitted and received powers, and overhead power consumption. Finally, the EEf is constrained to many quality of service (QoS) metrics, including number of resource blocks, total latency and minimum user's data rate.&lt;/span&gt;&lt;/p&gt;

Low-Cost Unified Pixel Converter from the MIPI DSI Packets into Arbitrary Pixel Sizes

The advance in semiconductors and image processing technologies has significantly improved visual quality, especially on mobile consumer devices. The devices require a low-cost and high-bandwidth interface to support various pixel formats on high-resolution displays; thus, the MIPI Alliance has proposed the industry-standard MIPI DSI (Display Serial Interface). The traditional implementation of DSI Rx has classified an incoming packet into three components, a header, a payload, and a checksum, by aligning the packet with the DSI PHY input width and then converting the payload into pixels. Its two-step approach has resulted in high implementation costs for supporting various pixels. This paper proposes a low-cost unified pixel converter, classifying each component and aligning the input payload into various pixel formats in only one step, thus achieving less area and lower power consumption overhead. Two terms are newly introduced for the proposal: a base and a remainder. The base size is the same as the DSI PHY input, and a remainder is a rest after the bases are aligned. The one-pixel size equals a sum of one or more bases and the remainder. The introduction allows us to implement the converter very straightforwardly due to the exact size of the base and the D-PHY input. Additionally, our approach does not require considering the header separately from the payload since the header size equals the base size. Therefore, the header detection unit is eliminated, thus reducing the complexity further. The proposed design was functionally verified in FPGA and synthesized through the Samsung 65 nm standard cell library. The synthesis result showed that the proposed design reduced by 25.7% in the area and 38.6% in the power consumption from the traditional design.

Design and Implementation of Shared Memory for Turbo and LDPC Code Interleaver

In 4G turbo and 5G LDPC, in order to realize a flexible, low-power, low-cost shared general-purpose block interleaving hardware module, it faces the challenges of interleaving structure integration, fewer gate circuits, parallel multistream operation, and switching between standards. Facing these challenges, after studying 3GPP TS 36.212 V15.4.0 and 3GPP TS 38.212 V15.4.0 protocols, common part of two major interleaving module standards is found. For the block interleave module in the rate matching of the 4G downlink turbo code and the bit interleave module after the rate matching of the 5G NR downlink LDPC code, this paper first designs a memory and implements the two codes interleaving on it. Then, based on the Altera Quartus prime platform and ModelSim for functional verification. Experimental results show that under SMIC 28 nm, operating frequency 50MHz, after synopsys synthesis, the memory module area is 0.17 μ m 2 , and the power consumption is 6.45 mW. Through the shared design, 32 bits parallel access, and switching between standards, the proposed scheme reduces the hardware cost, power consumption, and clock overhead, and improves the flexibility of 4G LTE and 5G NR communication downlink hardware implementation.

A dual mode self-test for a stand alone AES core.

Advanced Encryption Standard (AES) is the most secured ciphertext algorithm that is unbreakable in a software platform's reasonable time. AES has been proved to be the most robust symmetric encryption algorithm declared by the USA Government. Its hardware implementation offers much higher speed and physical security than that of its software implementation. The testability and hardware Trojans are two significant concerns that make the AES chip complex and vulnerable. The problem of testability in the complex AES chip is not addressed yet, and also, the hardware Trojan insertion into the chip may be a significant security threat by leaking information to the intruder. The proposed method is a dual-mode self-test architecture that can detect the hardware Trojans at the manufacturing test and perform an online parametric test to identify parametric chip defects. This work contributes to partitioning the AES circuit into small blocks and comparing adjacent blocks to ensure self-referencing. The detection accuracy is sharpened by a comparative power ratio threshold, determined by process variations and the accuracy of the built-in current sensors. This architecture can reduce the delay, power consumption, and area overhead compared to other works.

Event-Driven Acquisition and Machine-Learning-Based Efficient Prediction of the Li-Ion Battery Capacity.

In almost all contemporary power systems, the battery is an elementary component, and it is routinely used in a variety of critical applications such as drones, avionics, and cell phones. Due to their superior characteristics compared to the concurrent technologies, Li-ion batteries are widely utilized. Since batteries are costly, their usage is closely monitored by battery management systems (BMSs). It ensures that batteries survive and serve longer. Modern BMSs’ are complex and sophisticated and can deal with hundreds of cells in a battery pack. It results in an increased processing resources requirement and can cause an overhead power consumption. The aim of this work is to improve current BMSs by redesigning their associative processing chain. It focuses on improving data collection, processing and prediction processes for Li-ion battery cell capacities. To prevent the processing of a large amount of unnecessary data, the classical sensing approach that is fix-rate is avoided and replaced by event-driven sensing (EDS) mechanism to digitize battery cell parameters such as voltages, currents, and temperatures in a way that allows for real-time data compressing. A new approach is proposed for event-driven feature extraction. The robust machine-learning algorithms are employed for processing the extracted features and to predict the capacity of considered battery cell. Results show a considerable compression gain with a correlation coefficient of 0.999 and the relative absolute error (RAE) and root relative squared error (RRSE) of 1.88% and 2.08%, respectively.

LC-TSL: A low-cost triple-node-upset self-recovery latch design based on heterogeneous elements for 22 nm CMOS

With the continuous scaling of CMOS feature sizes, single event triple-node-upset (TNU) induced by charge sharing has become a serious reliability issue. This paper presents a low-cost triple-node-upset self-recovery latch (LC-TSL) which is composed of N-elements, P-elements and C-elements. The LC-TSL utilizes a two-dimensional feedback array composed of four rows and four columns to achieve triple-node-upset recovery. It utilizes high-speed transmission path to achieve high performance and clock-gating to reduce power consumption. The extensive simulation results show that the LC-TSL achieves high speed, low power consumption and 100% TNU recovery. Compared with the average of previous eight hardened latches, the LC-TSL reduces the delay by 78.59% and reduces the power-delay-product by 79.69%, while only increases 15.15% area overhead and 15.38% power consumption overhead. Compared with TNU self-recoverable latches, the LC-TSL is the best in terms of area, delay, and PDP. The LC-TSL achieves TNU-recovery ability and low cost overhead, and it is insensitive to voltage and temperature variations.

Design of High-Reliability Memory Cell to Mitigate Single Event Multiple Node Upsets

As technology scaling down, the sensitivity of SRAM cells to radiation-induced Single Event Upsets (SEUs) increases, and Single Event Multiple Node Upsets (SEMNUs) due to charge sharing has also become one of the major concerns in memory cell designs. In this paper, a high-reliability radiation hardened memory cell (RH-14T) is proposed to mitigate SEMNUs. SPICE simulations and 3D technology computer aided design mixed-mode simulations were performed to verify the high robustness of the RH-14T cell to SEUs. Compared with previous radiation hardened memory cells, the proposed RH-14T cell has similar read access time, smaller write access time, and the read access time and write access time are less sensitive to process variations. The Read Static Noise Margin (RSNM) and Write Margin (WM) of the RH-14T cell are larger than those of the unhardened conventional 6T SRAM cell. The improvement of reliability is often a trade-off with area, power consumption and performance. In order to achieve high reliability, the RH-14T cell employs more transistors, so it has 1.5 times the power consumption overhead of 6T and a larger area penalty.

LoRaWAN ESL for Food Retail and Logistics

Electronic shelf labels (ESL, or electronic price tag) are used by retailers for displaying product pricing on shelves substituting printed price tags; each ESL can display not only the price, but also text, and images, and can be remotely updated, configured, and programmed from a central server. Additionally, the emerging IoT paradigm, allows to expand the application horizon. Firstly, this work presents an analysis on how the use of Cloud-connected, intelligent, ESLs can improve food logistics in the complex scenarios of medium and large cities. Then, a low-cost ESL device, using an electronic ink (e-ink) display and the LoRaWAN protocol to communicate with the central server, aimed at price display and innovative applications in food retail and logistics, is presented. Several current consumption and communication distance measurements are shown, and the design and configuration space are explored to optimize battery life and communication reliability in the different food distribution scenarios. The proposed ESL is powered with a 500mA ·h LiMnO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> battery that can last for >8 years in a typical application, considering it communicates with a central server once per hour. The developed price tag can dynamically update the price and information for the customer, which in the case of food can be used to minimize spoilage and can easily upgraded to incorporate sensors or smartphone interaction to develop innovative food logistics and marketing practices. Finally, a LoRaWAN time-slot allocation strategy is presented, to minimize collisions when thousand nodes are connected to a single gateway, with a minimum power consumption overhead.

A 400 mV 160 nW/Ch Compact Energy Efficient ∆Σ Modulator for Multichannel Biopotential Signal Acquisition System.

Analog to digitalconverter circuit design for biomedical systems with multiple recording channels presents challenges in high density and very low power consumption. Passive integrator and loop-filter based delta-sigma modulators (DSMs) have been recently reported for ultra-low-power and highly energy-efficient data converters for multi-channel biopotential acquisition. However, these modulators rely on a very high oversampling ratio (OSR) to achieve the target resolution. Higher OSR leads to higher power consumption in the modulator and the digital low-pass and decimation filter succeeding the DSM. We present a low OSR passive integrator-based DSM in this work by relying on a duty-cycled resistor (DCR). DCR enables the realization of large time constants in the already passive loop-filter, with minimal area and overhead power consumption. This leads to design of DSMs that are highly area, power and energy-efficient, suitable for multi-channel biopotential recording systems. We demonstrate a second order, duty-cycled passive integrator based CTDSM in a 65 nm CMOS technology for a 10 kHz biopotential bandwidth. Measurement results show that the fabricated design achieves an SNDR/DR of 56.36/63.1 dB while consuming only 160 nW power with an OSR of 32 and occupies an area of 0.035 mm 2 with a state-of-the-art energy efficiency of 14.9 fJ/conv. In-vitro and in-vivo measurements are provided to further demonstrate the operation of the proposed DSM.

Multifrequency Data Parallel Spin Wave Logic Gates

By their very nature, Spin Waves (SWs) with different frequencies can propagate through the same waveguide without affecting each other, while only interfering with their own species. Therefore, more SW encoded data sets can coexist, propagate, and interact in parallel, which opens the road towards hardware replication free parallel data processing. In this paper, we take advantage of these features and propose a novel data parallel spin wave based computing approach. To explain and validate the proposed concept, byte-wide 2-input XOR and 3-input Majority gates are implemented and validated by means of Object Oriented MicroMagnetic Framework (OOMMF) simulations. Furthermore, we introduce an optimization algorithm meant to minimize the area overhead associated with multifrequency operation and demonstrate that it diminishes the byte-wide gate area by 30% and 41% for XOR and Majority implementations, respectively. To get inside on the practical implications of our proposal we compare the byte-wide gates with conventional functionally equivalent scalar SW gate based implementations in terms of area, delay, and power consumption. Our results indicate that the area optimized 8-bit 2-input XOR and 3-input Majority gates require 4.47x and 4.16x less area, respectively, at the expense of 5% and 7% delay increase, respectively, without inducing any power consumption overhead. Finally, we discuss factors that are limiting the currently achievable parallelism to 8 for phase based gate output detection and demonstrate by means of OOMMF simulations that this can be increased 16 for threshold based detection based gates.

Power Oriented Optimization for the Defect-Tolerant Mapping of CMOL Circuits

<p indent=0mm>Aiming at the power consumption increase problem from the defects of CMOS/nanowire/ molecular hybrid (CMOL) circuits, a defect-tolerant mapping method based on cell limitation is proposed. First, the power consumption model of defect pairs is established and the effect of different mapping patterns of the defect pairs on power consumption is analyzed. Then, the use of power hungry cells is restricted and the power consumption constraint is set to reduce the power consumption overhead caused by the high cost mapping patterns. Finally, the modified genetic algorithm is chosen to implement the defect-tolerant mapping of CMOL circuits. The ISCAS benchmarks are tested for verification. The experimental results demonstrated that the proposed method effectively reduces the power consumption and area of CMOL circuits on the basis of successful defect-tolerance, with better optimization of solution speed.