Abstract

By their very nature, Spin Waves (SWs) with different frequencies can propagate through the same waveguide without affecting each other, while only interfering with their own species. Therefore, more SW encoded data sets can coexist, propagate, and interact in parallel, which opens the road towards hardware replication free parallel data processing. In this paper, we take advantage of these features and propose a novel data parallel spin wave based computing approach. To explain and validate the proposed concept, byte-wide 2-input XOR and 3-input Majority gates are implemented and validated by means of Object Oriented MicroMagnetic Framework (OOMMF) simulations. Furthermore, we introduce an optimization algorithm meant to minimize the area overhead associated with multifrequency operation and demonstrate that it diminishes the byte-wide gate area by 30% and 41% for XOR and Majority implementations, respectively. To get inside on the practical implications of our proposal we compare the byte-wide gates with conventional functionally equivalent scalar SW gate based implementations in terms of area, delay, and power consumption. Our results indicate that the area optimized 8-bit 2-input XOR and 3-input Majority gates require 4.47x and 4.16x less area, respectively, at the expense of 5% and 7% delay increase, respectively, without inducing any power consumption overhead. Finally, we discuss factors that are limiting the currently achievable parallelism to 8 for phase based gate output detection and demonstrate by means of OOMMF simulations that this can be increased 16 for threshold based detection based gates.

Highlights

  • The amount of row data has rapidly increased in the last few decades due to the information technology unprecedented growth

  • Different technologies, e.g., graphene[7,8,9,10,11], memristor[12,13,14,15,16], spintronics[17,18,19,20,21] have been explored in an attempt to meet the exponentially increasing computing market demands[22]. While each of these alternative technologies exhibits both strong and weak points, spintronics on its Spin Wave (SW) flavour seems to have a great potential to meet market needs[22] due to its: (i) Ultra-low power consumption as no charge movements are required in order to perform calculations, (ii) acceptable delay, (iii) down to nm range scalability, and (iv) natural support for data parallelism enabled by the fact that SWs of different frequency can coexist and selectively interact within the same waveguide

  • As expected same-frequency SW pairs interfere without affecting the other SWs and this is clear from Figure 7, which indicates that 8 different frequencies components exist without distorting each-other in the Fast Fourier Transform (FFT) amplitude spectrum for all the considered input combinations

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Summary

INTRODUCTION

The amount of row data has rapidly increased in the last few decades due to the information technology unprecedented growth. This suggests that if each input pair (ai, bi) is encoded with fi frequency SWs, XOR(A, B) can be potentially evaluated with one instead of n XOR gates This approach has been pursued in[42], which introduces a Majority gate structure able to simultaneously process 3 data set encoded at 3 different frequencies. Design and validation of 8-bit data parallel in-line Spin Wave logic gates: 8-bit 3-input Majority and 2-input XOR gates are instantiated and validated by means of Object Oriented MicroMagnetic Framework (OOMMF) simulations. Performance assessment and comparison with SW state-of-the-art: The proposed 8-bit 3-input Majority and 2-input XOR gates require 4.47x and 4.16x less area, respectively, when compared with functionally equivalent scalar SW gate based implementations, at the expense of 5% and 7% delay penalty, respectively, and no power consumption overhead.

SW BASED COMPUTING BACKGROUND
F2 Fn F1 F2 Fn F1 F2 Fn
Simulation Platform
Simulation Parameters
Performed Simulations
SIMULATION RESULTS AND DISCUSSION
Simulation Results
Performance Evaluation
Fan-in and Geometrical Scalability
Practically Achievable Parallelism
Variability and Thermal Noise Effects
CONCLUSIONS
Full Text
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