Abstract

This paper presents a 2-output Spin-Wave Programmable Logic Gate structure able to simultaneously evaluate any pair of AND, NAND, OR, NOR, XOR, and XNOR Boolean functions. Our proposal provides the means for fanout achievement within the Spin Wave computation domain and energy and area savings as two different functions can be simultaneously evaluated on the same input data. We validate our proposal by means of Object Oriented Micromagnetic Framework (OOMMF) simulations and demonstrate that by phase and magnetization threshold output sensing AND, OR, NAND, NOR and XOR and XNOR functionalities can be achieved, respectively. To get inside into the potential practical implications of our approach we use the proposed gate to implement a 3-input Majority gate, which we evaluate and compare with state of the art equivalent implementations in terms of area, delay, and energy consumptions. Our estimations indicate that the proposed gate provides 33% and 16% energy and area reduction, respectively, when compared with spin-wave counterpart and 42% energy reduction while consuming 12x less area when compared to a 15 nm CMOS implementation.

Highlights

  • During the past decades, the human society experienced an information technology revolution that resulted in a huge increase of easy available raw data, which processing requires efficient computing platforms ranging from high-performance clusters to simple Internet of Things (IoT) nodes[1,2]

  • This paper presents a 2-output Spin-Wave Programmable Logic Gate structure able to simultaneously evaluate any pair of AND, NAND, OR, NOR, XOR, and XNOR Boolean functions

  • Our estimations indicate that the proposed gate provides 33% and 16% energy and area reduction, respectively, when compared with spin-wave counterpart and 42% energy reduction while consuming 12x less area when compared to a 15 nm CMOS implementation

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Summary

INTRODUCTION

The human society experienced an information technology revolution that resulted in a huge increase of easy available raw data, which processing requires efficient computing platforms ranging from high-performance clusters to simple Internet of Things (IoT) nodes[1,2]. The current controlled Mach-Zehnder interferometer was employed to construct a NOT gate, which is considered to be the first experimental work to implement logic gates using spin-waves[9]. Due to SW interaction way of operation, all of the reported logic gate designs cannot provide fan-out support, which is an essential gate feature for the effective implementation of larger circuits. This paper solves the above limitation and proposes a 2-output Programmable Logic Gate (PLG). Design of 2-input 2-output PLG: Two logic functions (including AND, NAND, OR, NOR, XOR and XNOR) can be implemented using a single 2-output structure. Demonstration of the superiority: The evaluations indicate that the proposed 2-output gate saves 33% of energy and 16% of area without incurring any delay penalty when compared with functionally equivalent designs based on state-of-the-art spin-wave gates.

SW TECHNOLOGY BACKGROUND
Proposed Programmable Logic Gate Structure
Logic Function Programming
SIMULATION SETUP AND EXPERIMENTS
PERFORMANCE EVALUATION AND DISCUSSION
Findings
CONCLUSIONS

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