Power Consumption Overhead Research Articles

Methods for Lowering the Power Consumption of OS-Based Adaptive Deep Brain Stimulation Controllers.

The identification of a new generation of adaptive strategies for deep brain stimulation (DBS) will require the development of mixed hardware–software systems for testing and implementing such controllers clinically. Towards this aim, introducing an operating system (OS) that provides high-level features (multitasking, hardware abstraction, and dynamic operation) as the core element of adaptive deep brain stimulation (aDBS) controllers could expand the capabilities and development speed of new control strategies. However, such software frameworks also introduce substantial power consumption overhead that could render this solution unfeasible for implantable devices. To address this, in this work four techniques to reduce this overhead are proposed and evaluated: a tick-less idle operation mode, reduced and dynamic sampling, buffered read mode, and duty cycling. A dual threshold adaptive deep brain stimulation algorithm for suppressing pathological oscillatory neural activity was implemented along with the proposed energy saving techniques on an energy-efficient OS, YetiOS, running on a STM32L476RE microcontroller. The system was then tested using an emulation environment coupled to a mean field model of the parkinsonian basal ganglia to simulate local field potential (LFPs) which acted as a biomarker for the controller. The OS-based controller alone introduced a power consumption overhead of 10.03 mW for a sampling rate of 1 kHz. This was reduced to 12 μW by applying the proposed tick-less idle mode, dynamic sampling, buffered read and duty cycling techniques. The OS-based controller using the proposed methods can facilitate rapid and flexible testing and implementation of new control methods. Furthermore, the approach has the potential to become a central element in future implantable devices to enable energy-efficient implementation of a wide range of control algorithms across different neurological conditions and hardware platforms.

A 13.56-MHz -25-dBm-Sensitivity Inductive Power Receiver System-on-a-Chip With a Self-Adaptive Successive Approximation Resonance Compensation Front-End for Ultra-Low-Power Medical Implants.

Battery-less and ultra-low-power implantable medical devices (IMDs) with minimal invasiveness are the latest therapeutic paradigm. This work presents a 13.56-MHz inductive power receiver system-on-a-chip with an input sensitivity of -25.4dBm (2.88μW) and an efficiency of 46.4% while driving a light load of 30μW. In particular, a real-time resonance compensation scheme is proposed to mitigate resonance variations commonly seen in IMDs due to different dielectric environments, loading conditions, and fabrication mismatches, etc. The power-receiving front-end incorporates a 6-bit capacitor bank that is periodically adjusted according to a successive-approximation-resonance-tuning (SART) algorithm. The compensation range is as much as 24pF and it converges within 12 clock cycles and causes negligible power consumption overhead. The harvested voltage from 1.7 V to 3.3V is digitized on-chip and transmitted via an ultra-wideband impulse radio (IR-UWB) back-telemetry for closed-loop regulation. The IC is fabricated in 180-nm CMOS process with an overall current dissipation of 750 nA. At a separation distance of 2 cm, the end-to-end power transfer efficiency reaches 16.1% while driving the 30-μW load, which is immune to artificially induced resonance capacitor offsets. The proposed system can be applied to various battery-less IMDs with the potential improvement of the power transfer efficiency on orders of magnitude.

WITHDRAWN: Battery sustainability algorithm based on shrink iteration and detection for women tracking system

Profuse crime against women is the most imperative problems for our country; it would affect people safety, women development and socio economic position. Leading the factors that cause’s high crime rate scenario is on cruelty against women, in the basis of critical scenario. To overcome the issue against women government put their efforts to reduce crime and increase citizen’s life quality. By developing applications and other sort of providing contact numbers but still crime against women is in increasing point on ratio. This problem is taken a considerable base problem in our current times: crime rate inference at the stranger level is eventually increased. Conventional influences to estimate crime rates in a particular area. With the prompt improvement of positioning knowledge and occurrence of mobile devices, a huge amount of modern urban data have been composed and such big data can provide new perspectives for understanding crime. The women tracking system using battery Sustainability algorithm have modulated with reduced power consumption and battery power management. The proposed system significantly reduces power consumption overhead and improves message passing among source and destination compared to existing DSR protocol agent.

A novel method for minimizing transient current test time by exploiting RES in SRAM

As technology advances, circuit density and complexity increases in integrated circuits which make the devices vulnerable to different types of manufacturing defects. In such cases, even the occurrence of a fault may be critical. Hence, ensuring Static random access memory (SRAM) reliability and quality with high priority is essential. In this paper, an innovative approach to SRAM testing—wavelet-based transient supply current testing with modified March sequence exploiting read equivalent stress (RES) is introduced for fault detection. The main contribution of this research work is the unique testing solution that ensures a minimum test time for the detection of open defects in SRAMs. In comparison with other techniques that solely rely on the hardware implementation for fault detection, the proposed technique reduces design parameters, such as the area overhead, power consumption, hardware complexity and performance overhead. The simulation results demonstrate that the proposed technique can provide high reliability and efficiency and reduce test time (25%) compared to other methods. A complete evaluation of the proposed technique in terms of the overall memory performance is presented in this work. The main objective of this study is to investigate the efficiency of wavelet-based transient current test in detecting all open defects targeted in this work in SRAMs amidst process variations. Moreover, the conventional test time of transient current test is minimized exploiting the effects of RES.

Event-Driven Coulomb Counting for Effective Online Approximation of Li-Ion Battery State of Charge

Lithium-ion batteries are deployed in a range of modern applications. Their utilization is evolving with the aim of achieving a greener environment. Batteries are costly, and battery management systems (BMSs) ensure long life and proper battery utilization. Modern BMSs are complex and cause a notable overhead consumption on batteries. In this paper, the time-varying aspect of battery parameters is used to reduce the power consumption overhead of BMSs. The aim is to use event-driven processing to realize effective BMSs. Unlike the conventional approach, parameters of battery cells, such as voltages and currents, are no longer regularly measured at a predefined time step and are instead recorded on the basis of events. This renders a considerable real-time compression. An inventive event-driven coulomb counting method is then presented, which employs the irregularly sampled data information for an effective online state of charge (SOC) determination. A high energy battery model for electric vehicle (EV) applications is studied in this work. It is implemented by using the equivalent circuit modeling (ECM) approach. A comparison of the developed framework is made with conventional fixed-rate counterparts. The results show that, in terms of compression and computational complexities, the devised solution surpasses the second order of magnitude gain. The SOC estimation error is also quantified, and the system attains a ≤4% SOC estimation error bound.

A Novel Matchline Scheduling Method for Low-Power and Reliable Search Operation in Cross-Point-Array Nonvolatile Ternary CAM

Cross-point-array nonvolatile ternary content-addressable memory (CPA nvTCAM) has recently emerged as an alternative to static random-access-memory-type TCAM, based on increased demands for high-capacity and low-power attributes. The CPA structure has various structural weaknesses such as the searchline (SL) combining with the dischargeline and the minimum line pitch of the matchline (ML). This study analyzes these weaknesses in detail for the first time and resolves the issues caused by these weaknesses using the proposed novel ML shield scheduling method with a matching probability-based flexible searching time technique (MLSS + MPFST). The proposed MLSS + MPFST resolves various issues and achieves greater than sixfold smaller cell size (8F <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) than the non-CPA nvTCAM with the smallest cell size. To verify the proposed schemes, the Monte Carlo HSPICE simulations were performed using a 22-nm industry-compatible bulk FinFET model parameter in 20-nm resistive memory technology at a circuit level, and the gem5 simulations were performed at a system level. The simulation results indicated that the CPA nvTCAM with the proposed MLSS + MPFST achieved a comparable search operation time of 1 ns and a slight power consumption overhead of 10% but an acceptable system performance overhead of less than 0.6% by resolving the various issues, compared with the non-CPA nvTCAM having the best performance.

Fault Detection Architectures for Inverted Binary Ring-LWE Construction Benchmarked on FPGA

Ring learning with errors (RLWE) is an efficient lattice-based cryptographic scheme that has worst-case reduction to lattice problem, conjectured to be quantum-hard. Ring-BinLWE is an optimized variant of RLWE problem using binary error distribution, resulting in highly-efficient hardware implementation. Efficient and low-complexity architectures in hardware, thwarting natural and malicious faults, are essential for lattice-based post-quantum cryptography (PQC) algorithms. In this brief, we explore efficient fault detection approaches for implementing the Ring-BinLWE problem. This brief, for the first time, investigates fault detection schemes for all three stages of RLWE encryption. Utilizing the stuck-at fault model, we employ recomputing with encoded operands schemes to achieve high error coverage. We simulate and implement our schemes on a field-programmable gate array (FPGA) platform. Our schemes provide low hardware overhead (area overhead of 15.74%, delay overhead of 7.74%, and power consumption overhead of 4.06%), with high error coverage, which can be suitable for resource-constrained as well as high-performance usage models.

Learning with Physical Noise or Errors

Hard learning problems have recently attracted significant attention within the cryptographic community, both as a versatile assumption on which to build various protocols, and as a potentially sound basis for lightweight (possibly side-channel and fault resistant) implementations. Yet, in this second case, a recurrent drawback of primitives based on the Learning Parity with Noise and Learning With Errors problems is their additional randomness requirements to generate noise or errors. In parallel, the move towards nanoscale devices renders modern implementations increasingly prone to various types of errors. As a result, inexact computing has emerged as a new paradigm to efficiently deal with the challenges raised by such erroneous computations, and mitigate the cost and power consumption overheads they cause. In this paper, we show that these cryptographic and electronic challenges can actually be turned into new opportunities, and provide an elegant solution one to the other. That is, we show that inexact implementations of inner product computations lead to a natural way to define new Learning with Physical Noise or Error assumptions, paving the way to more efficient and physically secure implementations, with potential interest for securing emerging Internet of Things applications.

SC-DDPL: A Novel Standard-Cell Based Approach for Counteracting Power Analysis Attacks in the Presence of Unbalanced Routing

In this paper we present the Standard Cell Delay-based Dual-rail Pre-charge Logic (SC-DDPL), a novel logic style which is able to counteract Power Analysis Attacks (PAAs) also in the presence of capacitive mismatch at the output of dual-rail gates. The SC-DDPL is based on a standard-cell design flow and it is suitable to be implemented on ASICs or FPGAs without any routing constraint on differential lines, supporting the Time Enclosed Logic protocol along with a DPL structure. The security provided by SC-DDPL has been firstly investigated in simulation on some basic logic gates, designed adopting a commercial 40nm CMOS technology. Simulated experiments have highlighted the capability of SC-DDPL gates to guarantee a high-level of security also in presence of extreme capacitive mismatch, exhibiting strongly reduced NED/NSD metrics, as well as a reduction of the FED, compared to a reference RTZ-based WDDL implementation. In order to compare the proposed logic against other state-of-the-art countermeasures we have implemented a 4bit PRESENT crypto-core adopting several logic styles, evaluating different security metrics on a 65nm Intel Cyclone-IV FPGA. Experimental results have confirmed that the SC-DDPL outperforms other gate-level countermeasures in terms of security metrics with a reasonable area and power consumption overhead.

Scalable Design Methodology and Online Algorithm for TSV-Cluster Defects Recovery in Highly Reliable 3D-NoC Systems

3D-Network-on-Chips exploit the benefits of Network-on-Chips and 3D-Integrated Circuits allowing them to be considered as one of the most advanced and auspicious communication methodologies. On the other hand, the reliability of 3D-NoCs, due to the vulnerability of Through Silicon Vias, remains a major problem. Most of the existing techniques rely on correcting the TSV defects by using redundancies or employing routing algorithms. Nevertheless, they are not suitable for TSV-cluster defects as they can either lead to costly area and power consumption overheads, or they may result in non-minimal routing paths; thus, posing serious threats to the system reliability and overall performance. In this work, we present a scalable and low-overhead TSV usage and design method for 3D-NoC systems where the TSVs of a router can be utilized by its neighbors to deal with the cluster open defects. An adaptive online algorithm is also introduced to assist the proposed system to immediately work around the newly detected defects without using redundancies. The experimental results show the proposal ensure less than 2 percent of the routers being disabled, even with 50 percent of the TSV clusters defects. The performance evaluations also demonstrate unchanged performances for real applications under 5 percent of cluster defects.

Cryogenic Memory Architecture Integrating Spin Hall Effect based Magnetic Memory and Superconductive Cryotron Devices

One of the most challenging obstacles to realizing exascale computing is minimizing the energy consumption of L2 cache, main memory, and interconnects to that memory. For promising cryogenic computing schemes utilizing Josephson junction superconducting logic, this obstacle is exacerbated by the cryogenic system requirements that expose the technology’s lack of high-density, high-speed and power-efficient memory. Here we demonstrate an array of cryogenic memory cells consisting of a non-volatile three-terminal magnetic tunnel junction element driven by the spin Hall effect, combined with a superconducting heater-cryotron bit-select element. The write energy of these memory elements is roughly 8 pJ with a bit-select element, designed to achieve a minimum overhead power consumption of about 30%. Individual magnetic memory cells measured at 4 K show reliable switching with write error rates below 10−6, and a 4 × 4 array can be fully addressed with bit select error rates of 10−6. This demonstration is a first step towards a full cryogenic memory architecture targeting energy and performance specifications appropriate for applications in superconducting high performance and quantum computing control systems, which require significant memory resources operating at 4 K.

Radiation Hardened Digital Direct Synthesizer With CORDIC for Spaceborne Applications

The Coordinate Rotation Digital Computer algorithm (CORDIC) is a simple mechanism to compute a set of elementary functions, such as trigonometric functions, using fixed-point devices. It is widely adopted, also in applications running in harsh environments such as space, where radiation is a cause of errors in nanoelectronic devices. A single event upset in a configuration bit of a Field Programmable Gate Array (FPGA) can completely change the behavior of the implemented circuit, so it is important to detect and reconfigure the FPGA when this happens. Dual modular redundancy is the typical method to detect errors in electronic circuits, but it has an important overhead in area and power consumption and it does not provide any additional functionality apart from the activation of the FPGA reconfiguration trigger in presence of error. This paper presents two ad-hoc techniques to protect the Digital Direct Synthesizer with CORDIC when it is implemented into an FPGA, with limited overhead in terms of area and power consumption when compared with the traditional solution. The first solution slightly increases the percentage of undetected errors, about 11%, reducing to almost half the area overhead of the circuit. The second solution introduces a trade-off between the percentage of error detection and the precision of the trigonometric output of the CORDIC by means of a polymorphic structure with lower area resources than the existing solutions. This last proposal allows the system to increase the precision of the digital synthesis signal under absence of errors or to activate the error protection in scenarios with external disturbances such as radiation.

Efficient fault-tolerant implementation of imprecision tolerant applications in nano scale error-prone VLSI technologies: A case study on fuzzy hardware

Emerging nano-level technologies provide very high device densities that facilitate high performance implementation of more complex applications. However, they also introduce new challenging reliability issues such as appearance of transient faults and concurrent occurrence of multiple faults in the circuits. Due to their nondeterministic nature, absolute detection and correction of all multiple concurrent transient faults in a circuit is a challenging task which becomes infeasible due to its very high space, time, or data redundancies as the number of concurrent faults increases. Fortunately, based to the emerging imprecise computing paradigm, it is not mandatory to detect and correct all the faults in a circuit when implementing an “Imprecision Tolerant” application, due to its inherent tolerance against imprecision. Thanks to this useful relaxation, this paper exploits the Relaxed Triple-Modular-Redundancy (RTMR) to trade the inherent robustness of the fuzzy applications against imprecision, to efficiently realize the defuzzification block as the most computation-intensive part of a Mamdani fuzzy processor in an unreliable technology. The traditional TMR is essentially developed to only cope with single permanent faults and the number of redundant components should be increased to N in an NMR system in order to handle (N-1)/2 concurrent faults. However, the experimental results show that RTMR can mitigate more numbers of concurrent transient faults with less overhead with respect to NMR. The synthesis results show that exploiting TMR causes higher area, delay, and power consumption overheads of up to 71%, 25%, and 63% respectively with respect to RTMR.

Efficient error detection and correction method for 1-out-of-3 binary signed digit adders

ABSTRACTBinary Signed Digit (BSD) number system has been extensively used in high-speed applications due to taking carry-free adders and high-speed multipliers. The 1-out-of-3 BSD encoding is an inherently fault-tolerant BSD encoding, which is a subset of m-out-of-n codes widely employed for error detection and correction. Although some fault-tolerant methods have been already proposed for 1-out-of-3 BSD adder, an efficient structure with both capabilities of fault detection and correction has not been introduced yet. In this paper, a 1-out-of-3 BSD adder with error detection and correction capabilities is presented. In spite of the negligible penalties in delay, power consumption, and area overhead, synthesis results show that more fault tolerance capability is achieved by the proposed method.

Sleepy-LRU: extending the lifetime of non-volatile caches by reducing activity of age bits

Emerging non-volatile memories (NVMs) are known as promising alternatives to SRAMs in on-chip caches. However, their limited write endurance is a major challenge when NVMs are employed in these highly frequently written caches. Early wear-out of NVM cells makes the lifetime of the caches extremely insufficient for nowadays computational systems. Previous studies only addressed the lifetime of data part in the cache. This paper first demonstrates that the age bits field of the cache replacement algorithm is the most frequently written part of a cache block and its lifetime is shorter than that of data part by more than 27 $$\times$$ . Second, it investigates the effect of age bits wear-out on the cache operation and shows that the performance is severely degraded after even a small portion of age bits become non-operational. Third, a novel cache replacement algorithm, so-called Sleepy-LRU, is proposed to reduce the write activity of the age bits with negligible overheads. The evaluations show that Sleepy-LRU extends the lifetime of instruction and data caches to 3.63 $$\times$$ and 3.00 $$\times$$ , respectively, with an average of 0.06% performance overhead. In addition, Sleepy-LRU imposes no area and power consumption overhead.

Linearity-Enhanced Doherty Power Amplifier Using Output Combining Network With Predefined AM–PM Characteristics

In this paper, a new method is proposed to synthesize a linearity-enhanced Doherty power amplifier (DPA) without deteriorating its efficiency. This method determines the combiner network parameters so that a predefined amplitude-to-phase (AM–PM) characteristic is produced while maintaining proper load modulation and consequently good back-off efficiency. The predefined AM–PM characteristic is chosen to be the inverse of the main transistor to enhance the overall DPA linearity. For proof-of-concept validation purposes, a linearity-enhanced DPA circuit prototype is designed to provide linear overall AM–PM characteristics over the frequency band of 4.7–5.3 GHz. Meanwhile, its input matching network is designed to minimize the amplitude-to-amplitude (AM–AM) distortion by properly selecting the source impedances. The measurement results of the DPA prototype under continuous-wave stimuli reveal AM–PM and AM–AM characteristics with maximum phase and gain compression/expansion below ±1° and ±0.25 dB, respectively, when the input power level is swept up to a saturation level of 39 dBm over 4.9–5.3 GHz. Furthermore, when driven with carrier aggregated signals with modulation bandwidths of up to 160 MHz and a peak-to-average power ratio equal to 7.4 dB, the DPA prototype maintains an adjacent channel leakage ratio of better than −40 dBc with a drain efficiency in the excess of 40% and an average output power of 32 dBm, without resorting to any additional linearization schemes. The proposed DPA methodology paves the road for the application of the DPA technique to 5G massive multiple-input and multiple-output transmitters with relaxed linearity requirements as it avoids the extra complexity and power consumption overhead associated with dedicated linearization schemes.

Combining containers and virtual machines to enhance isolation and extend functionality on cloud computing

Virtualization technology is the underlying element of cloud computing. Traditionally, cloud computing has employed virtual machines to distribute available resources and provide isolated environments among users. Multiple virtual machines, with their own operating system and services, can be deployed and run simultaneously on the same physical machine on the cloud infrastructure. Recently, a more lightweight virtualization technology is being rapidly adopted and it is based on containers. A key difference between virtual machines and containers, is that containers share the same underlying operating system.In this work, we studied the combination of these two virtualization technologies by running containers on top of virtual machines. This synergy aims to enhance containers’ main drawback, which is isolation and, among others, to simplify the system management and upgrade, and to introduce the new functionalities of containerized applications to virtual machines. The benefits of this method have been recognized by big cloud companies, which have been employing this approach for years.With this paper, we aimed to present the advantages of running containers on virtual machines and to explore how various virtualization techniques and configurations affect the performance of this method. Although, in bibliography there are a few papers that used this method partially to conduct experiments, there is not any research which considers this method from our integral aspect of view. In this study, we ran Docker containers and evaluated their performances, not only on KVM and XEN virtual machines, but also we ran Linux containers on Windows Server. We adopted an empirical approach, to quantify the performance overhead introduced by the additional virtualization layer of virtual machines, by executing various benchmarks and deploying real world applications as use cases. Furthermore, we presented for first time, how isolation is applied on virtual machines and containers, we evaluated different operating systems optimized to host containers, mechanisms of storing persistent data and, last but not least, we experimentally quantified the power and energy consumption overhead of containers running on virtual machines.

An efficient weighted trust‐based malicious node detection scheme for wireless sensor networks

SummaryThe aim of wireless sensor networks (WSNs) is to gather sensor data from a monitored environment. However, the collected or reported information might be falsified by faults or malicious nodes. Hence, identifying malicious nodes in an effective and timely manner is essential for the network to function properly and reliably. Maliciously behaving nodes are usually detected and isolated by reputation and trust‐based schemes before they can damage the network. In this paper, we propose an efficient weighted trust‐based malicious node detection (WT‐MND) scheme that can detect malicious nodes in a clustered WSN. The node behaviors are realistically treated by accounting for false‐positive and false‐negative instances. The simulation results confirm the timely identification and isolation of maliciously behaving nodes by the WT‐MND scheme. The effectiveness of the proposed scheme is afforded by the adaptive trust‐update process, which implicitly performs trust recovery of temporarily malfunctioning nodes and computes a different trust‐update factor for each node depending on its behavior. The proposed scheme is more effective and scalable than the related schemes in the literature, as evidenced by its higher detection ratio (DR) and lower misdetection ratio (MDR), which only slightly vary with the network's size. Moreover, the scheme sustains its efficient characteristics without significant power consumption overheads.

A New ASIC Structure With Self-Repair Capability Using Field-Programmable Nanowire Interconnect Architecture

Total ionizing dose tolerance is one of the essential features of the electronic devices used to control and monitor the vital operations in extreme environments. Most of today’s commercial off-the-shelf systems do not have this capability unless they are shielded with at least 10 cm of tungsten. Hence, application-specific integrated circuits (ASICs) are developed to achieve the desired performance in extreme environments. In this paper, a new ASIC structure with self-repair capability has been proposed using the field-programmable nanowire interconnect architecture. Our proposed structure includes a nonprogrammable part as circuit functionality and a reconfigurable part to improve the circuit reliability. The performance of the proposed structure is compared with some static and dynamic fault-tolerant approaches. According to the simulation results, the proposed structure can tolerate several permanent faults during the run time with minimum delay, power consumption, and area overhead.

Viola: Trustworthy Sensor Notifications for Enhanced Privacy on Mobile Systems

Modern mobile systems such as smartphones, tablets, and wearables contain a plethora of sensors such as camera, microphone, GPS, and accelerometer. These sensors can capture extremely sensitive and private information about the user including daily conversations, photos, videos, and visited locations, raising important privacy concerns. To address these concerns, we present Viola , our design and implementation of trustworthy sensor notifications , which use indicators such as LED to inform the user unconditionally when the sensors are on. We deploy Viola’s runtime monitor in low-level system software, e.g., in the operating system kernel or in the hypervisor . Moreover, we use formal verification methods to prove the functional correctness of the compilation of our invariant checks from a high-level language. We demonstrate that Viola incurs almost no overhead to the sensor’s performance and incurs only small power consumption overhead. Compared to our previous paper on Viola [1] , we present three important enhancements. First, we design, implement, and evaluate two-way sensor notifications , which guarantee that a sensor notification can be triggered if and only if the corresponding sensor is used. Second, we identify and add protection against concurrency attacks in Viola. Third, we implement Viola for an additional sensor and indicator combination.