Cryogenic Memory Architecture Integrating Spin Hall Effect based Magnetic Memory and Superconductive Cryotron Devices

Minh-Hai Nguyen,David Mcallister,Andrew P Wagner,Amir Jafari-Salim,Sean R Cheng,Brenden Butters,Sriharsha V Aradhya,Leonardo Ranzani ,Lijun Zhu,Shengjie Shi,Guilhem Ribeill ,Oleg A Mukhanov ,Karl K Berggren,Emily Toomey,Marco Colangelo,Patrick Truitt ,Graham E Rowlands,Reza Baghdadi,Daniel Yohannes,R A Buhrman ,Martin V Gustafsson,Rich Lazarus,Thomas A Ohki

doi:10.1038/s41598-019-57137-9

Abstract

One of the most challenging obstacles to realizing exascale computing is minimizing the energy consumption of L2 cache, main memory, and interconnects to that memory. For promising cryogenic computing schemes utilizing Josephson junction superconducting logic, this obstacle is exacerbated by the cryogenic system requirements that expose the technology’s lack of high-density, high-speed and power-efficient memory. Here we demonstrate an array of cryogenic memory cells consisting of a non-volatile three-terminal magnetic tunnel junction element driven by the spin Hall effect, combined with a superconducting heater-cryotron bit-select element. The write energy of these memory elements is roughly 8 pJ with a bit-select element, designed to achieve a minimum overhead power consumption of about 30%. Individual magnetic memory cells measured at 4 K show reliable switching with write error rates below 10−6, and a 4 × 4 array can be fully addressed with bit select error rates of 10−6. This demonstration is a first step towards a full cryogenic memory architecture targeting energy and performance specifications appropriate for applications in superconducting high performance and quantum computing control systems, which require significant memory resources operating at 4 K.

Highlights

Since the invention of the integrated circuit, the exponential increase in computing predicted by Moore’s law has made high performance computing (HPC) an essential driver for technological and scientific advances
As seen in the spin-Hall-effect based magnetic tunnel junction (SHE-MTJ) stack illustrated in Fig. 2(a), a thin Hf layer of 0.5 nm thick is inserted between the channel and the MTJ to suppress the Gilbert magnetic damping caused by spin pumping[36]
We have experimentally demonstrated the successful integration of SHE-based MRAM technology and the superconductive hTron bit-selects and drivers in a 4 × 4 memory array architecture which can be triggered by current signals as low as 100 μA, compatible with SFQ DC/RO control circuits

Summary

Introduction

Since the invention of the integrated circuit, the exponential increase in computing predicted by Moore’s law has made high performance computing (HPC) an essential driver for technological and scientific advances. Superconducting computers have long been a strong candidate for such “more than Moore” computing with the potential of two orders of magnitude lower power consumption than CMOS technology, even including the cost of cryogenic cooling power[3] This large advantage is due to near-lossless signal propagation along superconducting wires, and the picosecond delay and atto-Joule switching energy of Josephson junctions (JJs). Achievements in cryogenic spin-valves[16,17] and magnetic tunnel junctions[18] (MTJs) have recently been reported with energy consumption per switching of a few tens of fJ Integrating these successfully demonstrated magnetic elements with superconducting circuitry becomes an appealing route in the pursuit of larger scale cryogenic memory. We successfully integrate the two components (SHE-MTJs and hTrons) into a 4 × 4 cryogenic memory array in which the SHE-MTJ memory elements are addressed via hTron bit-select, row and column drivers

Methods

Results

Conclusion