Polynomial Basis Multiplier Research Articles

Input-Latency Free Versatile Bit-Serial GF(2 m ) Polynomial Basis Multiplication

Cryptography and error correction codes are widely used for information security and data integrity services in modern digital computing and communications systems. A number of standardized and published cryptography, and error correction algorithms utilize arithmetic operations over <inline-formula> <tex-math notation="LaTeX">$\text {GF}(2^{m})$ </tex-math></inline-formula>. The polynomial basis (PB) representation of <inline-formula> <tex-math notation="LaTeX">$\text {GF}(2^{m})$ </tex-math></inline-formula> elements is suitable for the support of multiple <inline-formula> <tex-math notation="LaTeX">$\text {GF}(2^{m})$ </tex-math></inline-formula> fields (that is, versatility). This article considers the problem of reduced hardware efficiency of versatile <inline-formula> <tex-math notation="LaTeX">$\text {GF}(2^{m})$ </tex-math></inline-formula> PB multipliers as a result of increased loading latency of the inputs and irreducible polynomial. In this context, to the best of our knowledge, this article proposes the first input-latency free versatile bit-serial <inline-formula> <tex-math notation="LaTeX">$\text {GF}(2^{m})$ </tex-math></inline-formula> multiplier using PB. The superiority of the proposed versatile PB multiplier is demonstrated for the case where the multiplication&#x2019;s inputs arrive serially in terms of higher output throughput and hardware efficiency compared to existing versatile PB and Gaussian normal basis (GNB) counterparts based on the application-specific integrated circuit (ASIC) and field-programmable gate array (FPGA) realizations, respectively. The proposed versatile PB multiplier improves hardware efficiency by factors of 1.8 and 2.5, respectively, compared to the versatile PB and versatile GNB counterparts.

Low-Delay FPGA-Based Implementation of Finite Field Multipliers

Arithmetic operations over binary extension fields GF(2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sup> ) have many important applications in domains such as cryptography, code theory and digital signal processing. These applications must be fast, so low-delay implementations of arithmetic circuits are required. Among GF(2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sup> ) arithmetic operations, field multiplication is considered the most important one. For hardware implementation of multiplication over binary finite fields, irreducible trinomials and pentanomials are normally used. In this brief, low-delay FPGA-based implementations of bit-parallel GF(2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sup> ) polynomial basis multipliers are presented, where a new multiplier based on irreducible trinomials is given. Several post-place and route implementation results in Xilinx Artix-7 FPGA for different GF(2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sup> ) finite fields are reported. Experimental results show that the proposed multiplier exhibits the best delay, with a delay improvement of up to 4.7%, and the second best Area×Time complexities when compared with similar multipliers found in the literature.

High-throughput area-delay-efficient systolic multiplier over GF(2m) for a class of trinomials

The paradigm of Edge Computing in Internet of Things (IoT) demands high-throughput implementations of IoT edge devices. Security algorithms used in these devices heavily use GF(2m) multiplications. Systolic structures for GF(2m) multipliers can offer high throughput rates along with other features such as regularity, concurrency, and modularity. Many systolic architectures for GF(2m) multiplier were proposed in the literature to achieve low area and time complexities. In this paper, we propose a high-throughput and low area-delay complexity systolic structure for the hardware realization of polynomial basis multiplication in GF(2m) for a class of trinomials. The complexity analysis shows that the proposed architecture results in achieving high throughput and less area-delay complexity compared with the existing polynomial basis multipliers in the literature. When compared with the best available multipliers, the multiplier realized using the proposed architecture achieves throughput improvement by 42% and reduction in area-delay product by 7% for m=409. Application specific integrated circuit (ASIC) implementations of the proposed multiplier and the best available multipliers confirm that the proposed multiplier outperforms the other multipliers. Hence, the proposed high-throughput area-delay-efficient multiplier can be employed in IoT edge devices.

Throughput/Area Efficient Implementation of Scalable Polynomial Basis Multiplication

In this paper, a scalable throughput/area efficient hardware implementation of polynomial basis multiplication based on a digit-digit structure is presented. To compute multiplication operation, both input operands of the multiplier proceed in digit or word level. This property leads to reduce hardware consumption and critical path delay because the number of hardware resources and the critical path of the structure depends on digit size, which is lower than field size. Also, in the proposed digit-digit structure, based on the change of input digit size from low digit size to high digit size, the number of clock cycles and input words are different. Therefore, the multiplier can be flexible and scalable for different cryptographic considerations such as low-area and high-speed implementations. The proposed architecture is simple, low-area and also the product of area and delay in the structure is reduced and compared with existing works. So, the multiplier can be suitable for lightweight elliptic curve cryptosystems. The proposed digit-digit polynomial basis multiplier, for different digit sizes, has been successfully verified and implemented over binary finite fields $$ {\mathbbm{F}}_{2^{163}} $$ and $$ {\mathbbm{F}}_{2^{233}} $$ on Virtex-4 XC4VLX100 and Virtex-5 XC5VLX110 FPGAs. The comparison results with other previous structures of the polynomial basis multiplication verify that the proposed method has better improvement in terms of hardware consumption and execution time.

LFSR-based Bit-Serial $GF(2^m)$ Multipliers using Irreducible Trinomials

In this article, a new architecture of bit-serial polynomial basis (PB) multipliers over the binary extension field $GF(2^m)$ G F ( 2 m ) generated by irreducible trinomials is presented. Bit-serial $GF(2^m)$ G F ( 2 m ) PB multiplication offers a performance/area trade-off that is very useful in resource constrained applications. The architecture here proposed is based on LFSR ( Linear-Feedback Shift Register ) and can perform a multiplication in $m$ m clock cycles with a constant propagation delay of $T_{A} + T_{X}$ T A + T X . These values match the best time results found in the literature for bit-serial PB multipliers with a slight reduction of the space complexity. Furthermore, the proposed architecture can perform the multiplication of two operands for $t$ t different finite fields $GF(2^m)$ G F ( 2 m ) generated by $t$ t irreducible trinomials simultaneously in $m$ m clock cycles with the inclusion of $t(m-1)$ t ( m - 1 ) flipflops and $tm$ t m XOR gates.

Efficient Lightweight Hardware Structures of Point Multiplication on Binary Edwards Curves for Elliptic Curve Cryptosystems

This paper presents efficient lightweight hardware implementations of the complete point multiplication on binary Edwards curves (BECs). The implementations are based on general and special cases of binary Edwards curves. The complete differential addition formulas have the cost of [Formula: see text] and [Formula: see text] for general and special cases of BECs, respectively, where [Formula: see text] and [Formula: see text] denote the costs of a field multiplication, a field squaring and a field multiplication by a constant, respectively. In the general case of BECs, the structure is implemented based on 3 concurrent multipliers. Also in the special case of BECs, two structures by employing 3 and 2 field multipliers are proposed for achieving the highest degree of parallelization and utilization of resources, respectively. The field multipliers are implemented based on the proposed efficient digit–digit polynomial basis multiplier. Two input operands of the multiplier proceed in digit level. This property leads to reduce hardware consumption and critical path delay. Also, in the structure, based on the change of input digit size from low digit size to high digit size the number of clock cycles and input words are different. Therefore, the multiplier can be flexible for different cryptographic considerations such as low-area and high-speed implementations. The point multiplication computation requires field inversion, therefore, we use a low-cost Extended Euclidean Algorithm (EEA) based inversion for implementation of this field operation. Implementation results of the proposed architectures based on Virtex-5 XC5VLX110 FPGA for two fields [Formula: see text] and [Formula: see text] are achieved. The results show improvements in terms of area and efficiency for the proposed structures compared to previous works.

Digit-Serial Versatile Multiplier Based on a Novel Block Recombination of the Modified Overlap-Free Karatsuba Algorithm

Overlap-Free Karatsuba Algorithm (OFKA) combined with block recombination approach (OFKABR) can improve the complexity of the original OFKA to obtain efficient implementation of polynomial basis multiplication over finite field $GF(2^{m})$ . In this paper, we have further proposed a modified OFKABR (MOFKABR) strategy to reduce the space and time complexities of the best-known method. The proposed strategy is also extended to obtain a low-complexity versatile multiplier, which is designed to support the generalized multiplication on a wider range of field size for $m_{1}\leq m\leq m_{\lambda }$ . Using the proposed MOFKABR approach, the proposed digit-serial versatile multiplier can achieve subquadratic space complexity when compared with the existing digit-serial versatile multipliers.

Fast Bit-Parallel Binary Multipliers Based on Type-I Pentanomials

In this paper, a fast implementation of bit-parallel polynomial basis (PB) multipliers over the binary extension field $GF(2^m)$ generated by type-I irreducible pentanomials is presented. Explicit expressions for the coordinates of the multipliers and a detailed example are given. Complexity analysis shows that the multipliers here presented have the lowest delay in comparison to similar bit-parallel PB multipliers found in the literature based on this class of irreducible pentanomials. In order to prove the theoretical complexities, hardware implementations over Xilinx FPGAs have also been performed. Experimental results show that the approach here presented exhibits the lowest delay with a balanced $Area\times Time$ complexity when it is compared with similar multipliers.

Efficient Implementation of Karatsuba Algorithm Based Three-Operand Multiplication Over Binary Extension Field

Three-operation multiplication (TOM) over binary extension field is frequently encountered in cryptosystems such as elliptic curve cryptography. Though digit-serial polynomial basis multipliers are usually preferred for the realization of TOM due to their efficient tradeoff in implementation complexity, the Karatsuba algorithm (KA)-based strategy is rarely employed to reduce the complexity further. Based on this reason, in this paper, we derive a novel low-complexity implementation of TOM based on a new KA-based digit-serial multiplier. The proposed TOM is obtained through two novel coherent interdependent efforts: 1) mapping an efficient KA-based algorithm into a novel digit-serial multiplier and 2) obtaining a new TOM structure through the novel derivation of the TOM algorithm. From the estimated results, it is shown that the proposed structure has significant lower area-time-complexities when compared with the existing competing TOMs. The proposed TOM is highly regular with low-complexity, and hence can be employed in many cryptographic applications.

Design and Implementation of a Sequential Polynomial Basis Multiplier over GF(2m)

Design and Implementation of a Sequential Polynomial Basis Multiplier over GF(2m)

Low space complexity CRT-based bit-parallel [formula omitted] polynomial basis multipliers for irreducible trinomials

This paper presents new space complexity records for the fastest parallel GF(2n) multipliers for about 22% values of n such that a degree-n irreducible trinomial f=un+uk+1 exists over GF(2). By selecting the largest possible value of k∈(n/2,2n/3], we further reduce the space complexities of the Chinese remainder theorem (CRT)-based hybrid polynomial basis multipliers. Our experimental results show that among the 539 values of n∈[5,999] such that f is irreducible for some k∈[2,n−2], there are 317 values of n such that k∈(n/2,2n/3]. For these irreducible trinomials, the space complexities of the CRT-based hybrid multipliers are reduced by 14.3% on average. As a comparison, the previous CRT-based multipliers considered the case k∈[2,n/2], and the improvement rate is 8.4% on average for only 290 values of n among these 539 values of n.

Efficient Bit-Parallel Systolic Polynomial Basis Multiplier over GF(28) based on Irreducible Polynomials

Objectives: Multiplication in Galois fields is used in many applications, especially in cryptography. Several algorithms and architectures are proposed in the literature to obtain efficient multiplication operations in Galois fields. Methods/ Statistical Analysis: In this paper, based on a modified interleaved modular multiplication algorithm, a bit-parallel systolic multiplier based on generic irreducible polynomials over Galois Field (GF (28)) is proposed. Theoretical hardware and speed complexity analysis is performed and the proposed multiplier is compared with other systolic multipliers available in the literature for irreducible polynomials. Findings: The proposed systolic multiplier achieves 21.23% reduction in hardware complexity when compared with the best multiplier among existing multipliers for m = 8. Applications/Improvements: The Field-Programmable Gate Array (FPGA) implementation results for the Advanced Encryption Standard (AES) and Two fish algorithms, incorporating the proposed multiplier and some existing designs, are also presented which indicates that the proposed multiplier achieves low area and low power consumption when compared with other systolic multipliers available in the literature.

Low‐delay AES polynomial basis multiplier

In this Letter, an efficient implementation of the bit-parallel polynomial basis (PB) multiplier over the binary field GF(28) generated by the type I irreducible pentanomial f(y) = y8 + y4 + y3 + y + 1 is presented. This pentanomial is especially important because it is used in the advanced encryption standard (AES). Therefore, any optimisation of the multiplier complexity over this finite field is very relevant because efficient AES implementation can be obtained. The bit-parallel multiplier here presented has the lowest delay known to date for similar multipliers based on this irreducible pentanomial.

Efficient implementation of bit‐parallel fault tolerant polynomial basis multiplication and squaring over GF(2 m )

This study presents the design and implementation of an efficient structure for fault tolerant bit-parallel polynomial basis multiplication and squaring over GF(2 m ), based on a similar strategy of Roving method with a minimum overhead. The Roving method is an efficient method for the circuits in which many similar and independent structures exist. The architectures of the polynomial basis multiplication and squaring over binary finite fields have inherent regularity in their subsections of the structures. Therefore, they are compatible to the applied version of Roving fault tolerant method. To generalise the proposed architecture, the multiplication and squaring operations are examined for different primitive polynomial, including general irreducible polynomials, irreducible pentanomials and irreducible trinomials. In the proposed design, the extracted common circuit has low hardware utilisation compared with that of the main circuit. The fault tolerant circuit is constructed by using three copies of the common circuit, a comparator and a voter circuit. The comparator and voter have parallel architectures with low critical path delays, which is a critical factor in any highly computational system. The design has been successfully verified and synthesised onVirtex-4 XC4VLX200 FPGA using Xilinx ISE 11. The results show an overall improvement in the speed and hardware usage compared with those of previous designs.

High-Speed Polynomial Basis Multipliers Over GF(2m) for Special Pentanomials

Efficient hardware implementations of arithmetic operations in the Galois field $GF(2^{m})$ are highly desirable for several applications, such as coding theory, computer algebra and cryptography. Among these operations, multiplication is of special interest because it is considered the most important building block. Therefore, high-speed algorithms and hardware architectures for computing multiplication are highly required. In this paper, bit-parallel polynomial basis multipliers over the binary field $GF(2^{m})$ generated using type II irreducible pentanomials are considered. The multiplier here presented has the lowest time complexity known to date for similar multipliers based on this type of irreducible pentanomials.

Versatile digit serial multipliers for binary extension fields

This work investigates the digit serial polynomial basis multipliers performing multiplication in multiple binary extension fields F2m1,F2m2,…,F2mλ. Designing such versatile multipliers encounters a number of difficulties. First of all, the element sizes of the supported fields are different from each other, and thus the elements are represented with different number of bits for each field. To deal with different sized elements, designs with left or right justified operands are investigated. Secondly, each field multiplication involves modular reduction with a different irreducible polynomial, and thus the complexity can increase rapidly with the number of supported fields λ. To prevent this, two methods are studied: Using sparse irreducible polynomials and unifying the modular reduction computation of the fields by choosing the irreducible polynomials suitably. Our work shows that multiple fields can be supported at the cost of an O(λ) increase in area and an O(λ) increase in time.

New Hardware Implementationsof WG&lt;inline-formula&gt;&lt;tex-math notation="LaTeX"&gt;$\bf {(29,11)}$&lt;/tex-math&gt; &lt;alternatives&gt;&lt;inline-graphic xlink:type="simple" xlink:href="elrazouk-ieq1-2346207.gif"/&gt;&lt;/alternatives&gt;&lt;/inline-formula&gt; and WG- &lt;inline-formula&gt;&lt;tex-math notation="LaTeX"&gt;$\bf {16}$&lt;/tex-math&gt;&lt;alternatives&gt; &lt;inline-graphic xlink:type="simple" xlink:href="elrazouk-ieq2-2346207.gif"/&gt;&lt;/alternatives&gt;&lt;/inline-formula&gt; StreamCiphers Using Polynomial Basis

The WG stream ciphers are based on the WG (Welch-Gong) transformation and possess proved randomness properties. In this paper we propose nine new hardware designs for the two classes of WG(29,11) and WG-16. For each class, we design and implement three versions of standard, pipelined and serial. For the first time, we use the polynomial basis (PB) representation to design and implement the WG(29,11) and WG-16. We consider traditional PB multiplier for the WG(29,11), and, the traditional and Karatsuba multipliers for the WG-16. For efficient field operations, we propose an irreducible trinomial for the WG(29,11). For the WG-16, a new formulation of its permutation which requires only 8 multipliers is introduced. In these designs, the multipliers in the transforms are further reduced by utilizing a novel computation for the trace of the multiplication of two field elements. We have implemented the proposed designs in ASIC using CMOS 65 nm technology. The results show that the proposed standard WG(29,11) consumes less area and slightly enhances the normalized throughput, compared to the existing counterparts. For the WG-16, throughput of the proposed pipelined instance outperforms the previous designs. Moreover, the speed of the proposed WG-16 designs meet the peak bit rates for the 4 G specifications.

Low Power Semi-systolic Architectures for Polynomial-Basis Multiplication over GF(2 m ) Using Progressive Multiplier Reduction

We present low area and low power semi-systolic array architectures for polynomial basis multiplication over GF(2m) using Progressive Multiplier Reduction Technique (PMR). These architectures are explored using linear and nonlinear techniques applied to the polynomial multiplication algorithm. The nonlinear techniques allow the designer, to control the processor workload and reduce the inter-processor communications. The semi-systolic architectures obtained have simple structure with local communication. ASIC implementations of our designs and comparable published designs show that the proposed scalable semi-systolic structures have less area complexity (56.8---94.6 %) and power consumption (55.2---84.2 %) except for a scalable design published by the same authors. However, one of the proposed scalable designs outperforms this design in terms of throughput by 73.8 %. This makes the proposed designs suited to embedded applications that require low power consumption and moderate speed.

Polynomial Basis Multiplier Using Cellular Systolic Architecture

ABSTRACTIn this study, we present a polynomial basis multiplication architecture based on cellular systolic hardware architecture for Montgomery multiplication over Galois fields by adopting a qualified Montgomery factor which is highly suitable for the design on our structures. At first, we propose a parallel computation algorithm which operates two independent computations. The algorithm is efficiently designed by reordering the sequence of the terms on the polynomial. Second, we construct an ideal architecture which is composed of two independent parts. Our architecture is possible to compute two parts simultaneously. Each part is composed of same cell structures so that it is easy to be generalized and scalable. Finally, we obtain a time-saved architecture in a large degree with high scalability.

An Efficient 5-Input Exclusive-OR Circuit Based on Carbon Nanotube FETs

An Efficient 5-Input Exclusive-OR Circuit Based on Carbon Nanotube FETs Ronak Zarhoun, Mohammad Hossein Moaiyeri, Samira Shirinabadi Farahani, and Keivan Navi The integration of digital circuits has a tight relation with the scaling down of silicon technology. The continuous scaling down of the feature size of CMOS devices enters the nanoscale, which results in such destructive effects as short channel effects. Consequently, efforts to replace silicon technology with efficient substitutes have been made. The carbon nanotube field- effect transistor (CNTFET) is one of the most promising replacements for this purpose because of its essential characteristics. Various digital CNTFET-based circuits, such as standard logic cells, have been designed and the results demonstrate improvements in the delay and energy consumption of these circuits. In this paper, a new CNTFET-based 5-input XOR gate based on a novel design method is proposed and simulated using the HSPICE tool based on the compact SPICE model for the CNTFET at the 32-nm technology node. The proposed method leads to improvements in performance and device count compared to the conventional CMOS-style design. Keywords: Nanotechnology, carbon nanotube field- effect transistor, CNTFET, high-performance circuits, CNTFET-based inverter, exclusive-OR gate, XOR gate. Manuscript received Jan. 13, 2013; revised Apr. 2, 2013; accepted Apr. 5, 2013. Ronak Zarhoun (phone: +98 2129904195, r.zarhoon@mail.sbu.ac.ir), Mohammad H. Moaiyeri (h_moaiyeri@sbu.ac.ir), and Samira S. Farahani (sa.shirinabadi@mail.sbu.ac.ir) are with the Nanotechnology and Quantum Computing Laboratory, Shahid Beheshti University, G.C., Tehran, Iran. Keivan Navi (corresponding author, navi@sbu.ac.ir, knavi@uci.edu) is with the Quantum Computing Laboratory, Shahid Beheshti University, G.C., Tehran, Iran, and is also with the Department of Electrical Engineering and Computer Science, University of California, Irvine, Irvine, CA, USA. ETRI Journal, Volume 36, Number 1, February 2014 http://dx.doi.org/10.4218/etrij.14.0113.0051 I. Introduction No one can imagine today’s world without the influence and power of computer technology, which dominates many aspects of people’s lives, from such simple details as cell phones to such important and critical projects as those in aeronautics. All computer-based technological improvements are possible through computational functions, which are made up of precise logic gates. Such logic gates as NOT, NAND, NOR, and XOR are the main building blocks of logical functions [1], [2]. Considering these gates, the XOR gate plays a significant role in computational processors with low-power purposes and arithmetic circuits [3], [4], such as full adder cells [5], [6]-[8], parity bit generators and parity checkers [9], multipliers such as the polynomial basis multiplier [10], and comparator circuits [8], [11], [12]. High-speed XOR gates are needed for summation of partial products in multiplier circuits, and they are also used in MUX modules in arithmetic circuits [12]. The most famous application of the XOR gate is in coding processes and data encryption or decryption, especially in AES (Advanced Encryption Standard) [1], which is sufficiently used in data communication. In design testing, it is used in built-in self-test structures [10] and is essential in cryptography [9], FPGAs, and high-performance structures. The XOR gate is even used in compressors, phase detectors, error detection, and error correction circuits [13]. Digital signal processor circuits with a logarithmic number system composed of several multipliers and adders benefits from XOR gates [14]. Moreover, the important role of this gate has even appeared in optical telecommunication networks for bit pattern recognition, operations related to address comparison, and so on [15], [16]. Design and development of XOR gates with conventional CMOS architecture is limited by the number of its inputs. As a Ronak Zarhoun et al.