Input-Latency Free Versatile Bit-Serial GF(2 m ) Polynomial Basis Multiplication

Abstract

Cryptography and error correction codes are widely used for information security and data integrity services in modern digital computing and communications systems. A number of standardized and published cryptography, and error correction algorithms utilize arithmetic operations over <inline-formula> <tex-math notation="LaTeX">$\text {GF}(2^{m})$ </tex-math></inline-formula>. The polynomial basis (PB) representation of <inline-formula> <tex-math notation="LaTeX">$\text {GF}(2^{m})$ </tex-math></inline-formula> elements is suitable for the support of multiple <inline-formula> <tex-math notation="LaTeX">$\text {GF}(2^{m})$ </tex-math></inline-formula> fields (that is, versatility). This article considers the problem of reduced hardware efficiency of versatile <inline-formula> <tex-math notation="LaTeX">$\text {GF}(2^{m})$ </tex-math></inline-formula> PB multipliers as a result of increased loading latency of the inputs and irreducible polynomial. In this context, to the best of our knowledge, this article proposes the first input-latency free versatile bit-serial <inline-formula> <tex-math notation="LaTeX">$\text {GF}(2^{m})$ </tex-math></inline-formula> multiplier using PB. The superiority of the proposed versatile PB multiplier is demonstrated for the case where the multiplication&#x2019;s inputs arrive serially in terms of higher output throughput and hardware efficiency compared to existing versatile PB and Gaussian normal basis (GNB) counterparts based on the application-specific integrated circuit (ASIC) and field-programmable gate array (FPGA) realizations, respectively. The proposed versatile PB multiplier improves hardware efficiency by factors of 1.8 and 2.5, respectively, compared to the versatile PB and versatile GNB counterparts.