Versatile digit serial multipliers for binary extension fields

Abstract

This work investigates the digit serial polynomial basis multipliers performing multiplication in multiple binary extension fields F2m1,F2m2,…,F2mλ. Designing such versatile multipliers encounters a number of difficulties. First of all, the element sizes of the supported fields are different from each other, and thus the elements are represented with different number of bits for each field. To deal with different sized elements, designs with left or right justified operands are investigated. Secondly, each field multiplication involves modular reduction with a different irreducible polynomial, and thus the complexity can increase rapidly with the number of supported fields λ. To prevent this, two methods are studied: Using sparse irreducible polynomials and unifying the modular reduction computation of the fields by choosing the irreducible polynomials suitably. Our work shows that multiple fields can be supported at the cost of an O(λ) increase in area and an O(λ) increase in time.