Polycrystalline Silicon Thin-film Transistors Research Articles

Flexible TFT backplane development for extremely small bending radius with organic ILD and novel TFT structures

AbstractA new flexible low‐temperature polycrystalline silicon thin film transistors (LTPS TFTs) on PI substrate with organic ILD layer, island TFT, and TFT channel perpendicular to stress direction was proposed. AMOLED display panel manufactured with organic ILD did not show any visible degradation of panel image after outward rolling cycles of 200,000 at rolling radius of 4 mm or inward folding cycles of 200,000 at folding radius of 1 mm. Another novel structure of TFT with channel perpendicular to stress direction significantly reduced change of threshold voltage of −0.03 V compared with change of threshold voltage of −0.6 V for TFT with channel parallel to stress direction for reliability test of high drain current (HDC) after 100,000 outward‐bending cycles at bending radius of 3 mm. After inward‐bending cycles of 200,000 at bending radius of 1 mm, reliability test results for TFT device with organic ILD layer showed that change of on‐current is 10.07% for hot carrier instability (HCI) test, change of threshold voltage −0.31 V for negative bias thermal instability (NBTI) test, change of threshold voltage −0.24 V for hysteresis test, and breakdown voltage of gate insulator 7.73 MV/cm, respectively, and these performances are similar to those of TFT device with inorganic ILD (SiNx).

Roles of Trap States in the Dynamic Degradation of Polycrystalline Silicon Thin-Film Transistors Under AC Gate Bias Stress

Roles of Trap States in the Dynamic Degradation of Polycrystalline Silicon Thin-Film Transistors Under AC Gate Bias Stress

High Reliability Tungsten-Doped Indium Zinc Oxide Thin Film Transistors for Display Applications

Recently, flat panel display technologies are based on amorphous silicon (a-Si), polycrystalline silicon (poly-Si) or amorphous oxide semiconductor (AOS) thin film transistors (TFTs) technology. In order to reach higher performance for ultra-high resolution display applications, the material selection for the channel layer is vital. AOS TFTs drawn lots of attention because of its advantages such as low leakage current, high driving current and high uniformity [1,3]. In this work, we presented a novel amorphous oxide semiconductor (AOS) material of gallium-free a-InWZnO thin film transistors (IWZO TFTs) which is very promising to be applied for ultra-high resolution display technology. Experiment In this work, we demonstrated the structure of a-IWZO TFTs processes. Figure 1 shows the schematic of the TFT cross-section. After growing a 550 nm thermal oxide layer as buffer layer, a 25-nm-thick of molybdenum was deposited by DC-sputter as the bottom gate electrode. A 10-nm-HfO2 was deposited by plasma-enhanced atomic layer deposition (PEALD) system as high-κ gate dielectric (GI). Then, post deposition annealing (PDA) was carried out to enhance the quality of the insulator layer. Next, an ultra-thin body a-IWZO was deposited by RF-sputter as channel layer. Finally, source and drain were defined by lift-off process and the gate contact via was etched by dry etching to finish the device fabrication. Result and Discussion Figure 1(b) shows the negative gate bias stress (NGBS) transfer curve (ID-VG) of a-IWZO TFTs with passivation layer. The experimental results have shown that passivation layer could keep the back channel of IWZO channel from exposing to oxygen and hydrogen from the atmosphere. Without the passivation layer, the back channel would contact moisture leading the diffused hydrogen atoms to fill oxygen vacancy sites and de-trap free carriers, causing the VTH shifts negatively. The ultra-thin a-IWZO TFTs with passivation layer exhibited a low subthreshold swing (S.S.) of 89.7 mV/dec, high on/off current ratio (ION/IOFF) of 2.1×107 and small threshold voltage shift (ΔVth) of -0.097 V during NGBS of -2MV/cm with 2000s. To sum up, the passivation layer could enhance the a-IWZO TFTs reliability. Reference [1] Kamiya, H. Hosono, NPG Asia Mater., vol. 2, pp. 15, 2010.[2] Nomura, H. Ohta, A. Takagi, T. Kamiya, M. Hirano, and H. Hosono, nature, vol. 432, no. 7016, pp. 488-492, 2004.[3] Y. Kuo, C. M. Chang, I. H. Liu, and P. T. Liu, Scientific reports, vol. 9, no. 1, pp. 1-7, 2019. Figure 1

Exploring Performance and Reliability Behavior of Nanosheet Channel Thin-Film Transistors under Independent Dual Gate Bias Operation

In this work, the polycrystalline-silicon (poly-Si) thin-film transistor with an independent dual-gate (IDG) structure and ultra-thin nanosheet channel (∼4 nm) is fabricated to investigate the impacts of different dual-gate operation modes on device performance and reliability. Compared to the single top-gate (TG) operation mode, the double-gate (DG) operation mode exhibits superior threshold voltage (VTH), subthreshold swing, and saturation current in the device. In addition, the DG operation mode also shows better reliability behavior of positive gate bias stress (PGS) due to the enhanced control capability of the gate voltage on the channel potential. Under the single TG operation mode, the independent back-gate voltage (VBG) can effectively modulate the device’s VTH to meet circuit design requirements. Using a fixed positive VBG can not only reduce the VTH of the device, but also decrease the damage caused by the PGS on the device due to the buried channel effect generated by the ultra-thin nanosheet channel, which increases the coupling capacitance thickness between the buried channel and the top-gate oxide layer. On the contrary, using a negative VBG will enhance the PGS degradation of TG. Consequently, the positive VBG is suggested to lower the VTH and improve the PGS of the device.

Reducing Leakage Current Using LTPS-TFT Pixel Circuit in AMOLED Smartwatch Displays

This work proposes a new pixel circuit that is operated at a low frame rate using low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs) for use in active-matrix organic light-emitting diode (AMOLED) smartwatch displays. The proposed circuit uses a new leakage-prevention method (LPM) to balance the off currents at the gate node of the driving TFTs, eliminating the drop of the driving voltage. Uniform OLED currents are thus generated throughout the extended emission period. Also, the OLEDs are all turned off except in the emission stage to suppress image flicker. To confirm the feasibility of the proposed pixel circuit, a 1.41-inch panel, based on the proposed circuit, is fabricated. Experimental results demonstrate that diminishing the off currents maintains the driving capability of the pixel circuit to stabilize the luminance of the fabricated panel. The exhibitions of red, green, blue, and white images at frame rates from 60 Hz to 15 Hz are uniform, verifying that the proposed pixel circuit with LPM has high potential for use in AMOLED smartwatch displays with a low frame rate.

Investigating DC and AC degradation behaviors to P-type low temperature polycrystalline silicon thin film transistor with fin-like structure

Currently, thin film transistor (TFT) based on planar structure is widely used in the applications of display panels. However, when the device is scaling-down, new device structures or novel materials should be introduced. In this work, the low temperature polycrystalline silicon (LTPS) TFT with fin-like structure is investigated. On the basis of electrical measurements, the device features good switching characteristics with low operating voltages. However, the I d–V g sweeping result exhibits off-state leakage, which is known as the gate-induced drain leakage (GIDL) current. The GIDL current is increased with the drain bias and the temperature increasing. To observe the GIDL current degradations, different gate biases with negative bias stress and positive bias stress are applied. The results show different degradation behaviors. In addition, bias stresses with DC and AC methods are also applied to verify the device reliability. Both threshold voltage (V t) shift and sub-threshold swing (S.S.) are also extracted to verify the degradations of the device. Finally, the physical models are also proposed to illustrate the degradation behaviors of the LTPS device with a fin-like structure, which can be beneficial to future related development of LTPS-based devices.

Performance and reliability enhancement of flexible low-temperature polycrystalline silicon thin-film transistors via activation-annealing temperature optimization

The high performance and reliability of low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) on flexible substrates need to be ensured for the proper operation of advanced flexible organic light-emitting diode (OLED) displays. However, due to the heat-sensitive components of flexible LTPS TFTs, their fabrication process faces challenges in the temperature management of its thermal treatment procedures such as activation annealing, which is an essential step in the in-line fabrication process of LTPS TFTs for activating dopants and reducing silicon lattice-related structural defects. In this work, we investigate the optimization of the activation-annealing process through the modulation of its process temperature. As the activation-annealing temperature was increased from 320 °C to 370 °C, the electrical characteristics and reliability of flexible LTPS TFTs improved owing to a decrease in the gate dielectric/channel interface and bulk channel defects. However, as the temperature was further increased to 420 °C, considerable degradations in device performance and reliability were observed due to a significant increase in the deep-level gate dielectric/channel interface and bulk channel defects. Physical analysis revealed that significant dehydrogenation, in which the breakage of Si−H bonds causes excess Si dangling bonds, occurred at 420 °C. This work shows that a fine temperature optimization of the activation annealing process is a necessary procedure for ensuring highly performant and reliable LTPS TFTs on flexible substrates.

P‐11: A Novel AMOLED Pixel Circuit using Double‐Gate LTPO TFTs for Variable Refresh Rate with Low Power Consumption

This paper proposes an Active Matrix Organic Light Emitting Diode (AMOLED) pixel circuit for Variable Refresh Rate (VRR) driving from 1Hz to 240Hz. The circuit is based on a double‐gate Low Temperature Polycrystalline Silicon and Oxide (LTPO) Thin Film Transistor (TFT) backplane. For low frame rate driving we used oxide TFTs as the Switching (SW) TFTs. Moreover, we applied double‐gate Low Temperature Polycrystalline Silicon (LTPS) process to the Driving (DR) TFT for compensation of the Threshold Voltage (Vth) by controlling the bottom gate bias at a high refresh rate. In this paper, operation principle and simulation results will be illustrated to demonstrate the performance of the proposed circuit.

A novel LTPO AMOLED pixel circuit and driving scheme for variable refresh rate

This paper proposes a novel pixel circuit and driving scheme that adopts low-temperature polycrystalline silicon and oxide thin-film transistors (LTPO TFTs) for mobile devices using active-matrix organic light-emitting diode (AMOLED) displays. The proposed pixel circuit and driving scheme provide uniform luminance and render flicker invisible at variable refresh rates (VRRs) from 1 to 120 Hz. Using the proposed pixel circuit with extended compensation time (tCOMP) improves the luminance uniformity at a high-frame rate. The proposed driving scheme applies a voltage to the driving TFTs (D-TFTs) higher than the programmed data voltage during the skip frame. This reduces the flicker caused by the hysteresis of D-TFTs during low-frame rate driving. A 6.0-inch quad high-definition (QHD) LTPO-based AMOLED display was fabricated using the new pixel circuit and driving scheme. Experimental results of the proposed pixel circuit show that the standard deviation of luminance was reduced from 0.056 to 0.008 by extending tCOMP from 2 to 8 µs. The flicker level was −51 dB, so there was no visual artifact during 1 Hz driving. A flicker-free LTPO-based AMOLED display with low power consumption is possible; driving can proceed in 1–120 Hz range.

Abnormal Degradation Behaviors Under Negative Bias Stress in Flexible p-Channel Low-Temperature Polycrystalline Silicon Thin-Film Transistors After Laser Lift-Off Process

This work investigates the abnormal phenomena that are observed in electrical characteristics under negative bias stress (NBS) in flexible p-channel low-temperature polycrystalline silicon thin-film transistors (p-channel LTPS TFTs) after TFTs being lifted off from a rigid substrate. During the lift-off process, mechanical strain accumulates in the buffer layer due to the unilateral force, thus resulting in the generation of defects in the buffer layer. Therefore, abnormal degradation behaviors in electrical characteristics of the lifted-off TFTs were observed during negative gate bias stress. A study on physical mechanisms is introduced to describe such abnormal phenomena, and it is confirmed that defects are produced in the buffer layer when the LTPS TFTs are lifted off. In addition, different device dimensions were discussed to support our proposed model. The findings in this work are supported by the discussion of electrical characteristics, trap state extraction, and COMSOL simulation.

Impact of Nanosheet Thickness on Performance and Reliability of Polycrystalline-Silicon Thin-Film Transistors With Double-Gate Operation

Impact of Nanosheet Thickness on Performance and Reliability of Polycrystalline-Silicon Thin-Film Transistors With Double-Gate Operation

Void-Defect Location Control of Laser-Crystallized Silicon Thin Films with Hole-Pattern

High-performance low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) have been developed for larger applications than flat panel displays (FPDs) such as three-dimensional integrated circuits (3D-ICs) and glass sheet computers. The crystallinity of poly-Si thin films has been the key factor determining TFTs’ performance. In this work, a void-defect location has been controlled by patterning amorphous silicon (a-Si) thin films with rectangular and square holes before crystallized by multiline continuous-wave laser beam to avoid the effect of void-defects on the TFTs’ performance. Instead of randomly appearing in the poly-Si thin films, void-defects were only observed at the backsides of the patterned holes. Interestingly, large crystal grains without void-defects were laterally crystallized at Si strips between holes. By observing the crystallinities of poly-Si thin film around the patterned holes, both the mechanism of the void formation and crystal growth based on temperature gradient was clarified.

Electrical Characteristics of Atmospheric-Pressure Plasma Enhanced Chemical Vapor Deposition Fabricated Indium-Gallium-Zinc-Oxide Thin-Film Transistors with In-Situ Hydrogenation and Neutral Beam Oxidation

Low temperature poly-crystalline silicon thin-film transistors (LTPS-TFTs) and indium-gallium-zinc-oxide TFTs (IGZO-TFTs) are potential candidates for future technology of various displays. Due to its simple manufacturing process, low cost and good uniformity, IGZO-TFTs have been developed as main stream display technology. From the viewpoint of device electrical characteristics, a-IGZO TFTs have better field-effect mobility (>10 cm2/V * s), larger Ion/Ioff ratio (>106), smaller subthreshold swing (S.S) and good stability. In this study, atmospheric-pressure PECVD (AP-PECVD) is used to deposit a-IGZO active layer, during the deposition process In-Situ hydrogenation is applied to enhance the layer characteristics. Also, the layer is then surface oxidation treated by neutral beam system (NBS). The optimal TFTs device characteristics is reached with In-Situ hydrogenation of H2 90 sccm, and surface oxidation of 400 W NBS treatment. The field-effect mobility is 34.05 cm2/V * s, threshold voltage is 1.74 V, subthreshold swing is 62 mV/decade, and current ratio Ion/Ioff is 2.04×107. Compared with conventional plasma, NBS used in this study provides charge-free plasma which could enhance device electric characteristics.

(Invited) Oxide TFT Applications: Principles and Challenges

The main advantage of the thin film transistor (TFT) is that it can be fabricated on non-wafer substrate independent of the size, flexibility, and morphology. All composing films of the TFT are deposited at the low temperature. Therefore, TFTs can be applied to a broad range of consumer, biological, chemical, and optical products that are difficult to fabricate with the wafer based MOSFETs.There are many reports on a-Si:H and poly-Si TFT applications in displays, imagers, sensors, drivers, flexible electronics, and circuits (1,2). In principle, oxide TFTs can be applied to similar products. However, since the device characteristics and compositing materials of the oxide TFT are different from those of the a-Si:H and poly- Si TFTs, as shown in Figure 1 and Table 1, there are advantages and disadvantages in former’s applications. In this presentation, oxide TFT applications in the following three areas will be discussed. Control of the attached device, such as pixel-driving in displays,Integrated circuits, such as drivers or inverters, andChanging of characteristics with environment, such as pH, optical, and temperature sensors. L. Antonuk, Chapt. 10, and Y. Kuo, Chapt. 11, Amorphous Silicon Thin Film Transistors, pp. 395-505, Kluwer Academic Publishers, 2004.B.-D. Choi, et al., Chapt. 11-13, Polycrystalline Silicon Thin Film Transistors, Y. Kuo Editor, pp. 360-495, Kluwer Academic Publishers, 2004.Kuo and G. W. Chang, ECS Trans, 64(10), 145-153 (2014). Figure 1

Degradation mechanisms for polycrystalline silicon thin-film transistors with a grain boundary in the channel under negative gate bias stress

The negative gate bias stress (NBS) reliability of n-type polycrystalline silicon (poly-Si) thin-film transistors (TFTs) with a distinct defective grain boundary (GB) in the channel is investigated. Results show that conventional NBS degradation with negative shift of the transfer curves is absent. The on-state current is decreased, but the subthreshold characteristics are not affected. The gate bias dependence of the drain leakage current at V ds of 5.0 V is suppressed, whereas the drain leakage current at V ds of 0.1 V exhibits obvious gate bias dependence. As confirmed via TCAD simulation, the corresponding mechanisms are proposed to be trap state generation in the GB region, positive-charge local formation in the gate oxide near the source and drain, and trap state introduction in the gate oxide.

P‐1.4: Analysis of the Hump Characteristics in Poly‐Si Thin Film Transistor & Process a method to suppress hump effect

In this study, we investigate the transfer characteristics of low‐temperature polycrystalline silicon(LTPS) thin film transistors(TFTs) often show a “hump” in subthreshold region. This effect can be attributed to the presence of an enhanced electrical field at edges of the active layer. To reduce the hump effect which is one of the critical issues in ploy‐Si TFT, we focus on crowding of gate fringing field at channel edge and suggest a modified structure of channel edge. Using dry etching process, change the polysilicon layer at the edge of the channel from a steep profile to a slightly flat profile. And we confirmed that the severity of the hump effect is directly related to the edge profile of the polysilicon.

Binary-Synaptic Plasticity in Ambipolar Ni-Silicide Schottky Barrier Poly-Si Thin Film Transistors Using Chitosan Electric Double Layer.

We propose an ambipolar chitosan synaptic transistor that effectively responds to binary neuroplasticity. We fabricated the synaptic transistors by applying a chitosan electric double layer (EDL) to the gate insulator of the excimer laser annealed polycrystalline silicon (poly-Si) thin-film transistor (TFT) with Ni-silicide (NiSi) Schottky-barrier source/drain (S/D) junction. The undoped poly-Si channel and the NiSi S/D contact allowed conduction by electrons and holes, resulting in artificial synaptic behavior in both p-type and n-type regions. A slow polarization reaction by the mobile ions such as anions (CH3COO− and OH−) and cations (H+) in the chitosan EDL induced hysteresis window in the transfer characteristics of the ambipolar TFTs. We demonstrated the excitatory post-synaptic current modulations and stable conductance modulation through repetitive potentiation and depression pulse. We expect the proposed ambipolar chitosan synaptic transistor that responds effectively to both positive and negative stimulation signals to provide more complex information process versatility for bio-inspired neuromorphic computing systems.

Electrical-performance and reliability improvement of flexible low-temperature polycrystalline silicon thin-film transistors via post-annealing process

We investigated the improvement methods of the electrical characteristics and reliability of flexible low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) by optimizing the annealing process. We investigated the effect of annealing on the device properties via electrical measurement and density-of-state (DOS) analysis. The annealing temperature should be reduced for flexible LTPS TFTs compared to rigid devices because the range of the thermal stability of flexible substrate is narrower than that of the glass substrate. As the activation annealing temperature (T a) decreased, the threshold voltage and field-effect mobility (μ FE) decreased, and the subthreshold swing (SS) increased. When the post-annealing temperature (T pa) decreased, μ FE increased, and the changes in the other parameters were negligible. The DOS decreased with an increase in T a and a reduction in T pa. These results originated from ineffective dopant activation and defect curing due to the lower T a and the enhanced hydrogen defect passivation at the lower T pa. Therefore, flexible LTPS TFTs with reduced T a values exhibited similar μ FE values and lower SS values when the post-annealing process was omitted. Furthermore, removing the post-annealing process improved the reliability of the flexible LTPS TFTs with reduced T a values under electrical stress. According to a hot-carrier instability analysis, defect passivation by hydrogen was more stable than defect curing with a higher T a. Consequently, although T a was low for flexible LTPS TFTs, the electrical performance and reliability could be improved by optimizing the post-annealing process.

Modeling of High-Current Polycrystalline Silicon Thin Film Transistors by Incorporating Buried Electrode

For display applications, high current and large on/off current ratio are pursued for driving and switching transistors. In this article, a thin film transistor (TFT) device incorporating a buried electrode is proposed, which enables increasing the driving current by reducing the channel length, with the channel length only at the drain side. This lateral short-channel TFT enables increasing the on-current while maintaining the field effect mobility, in comparison to our experimental short-channel vertical TFT structure. Another advantage of the proposed structure lies in the suppression of the Schottky barrier at the source and drain contacts when using high-work-function source/drain contacts for an N-type TFT, with an increased on/off current ratio reaching approximately 106. The suppression of Schottky barrier at the source/drain has been verified by the contact resistance measurements. Even though high driving current is obtained, the off-current is still high due to the weakened electric field at the source/drain sides and needs to be further optimized.

Simplified EKV model parameter extraction in polysilicon MOSFETs

We present an easy but effective method to extract the four parameters of the simplified Enz–Krummenacher–Vittoz (sEKV) MOSFET model. The procedure, which is based on direct lateral optimization, is tested using measurements from experimental polycrystalline silicon Thin Film Transistors (TFTs) of various channel lengths and widths. We demonstrate that this basic MOSFET model is able to reasonably describe the saturation transfer characteristics of these polysilicon TFTs. Furthermore, we evaluate the computational adeptness for extracting the four sEKV parameters of the lateral optimization fitting procedure as compared to the more traditional vertical optimization one.