Polycrystalline Silicon Thin-film Transistors Research Articles

Effect of Ultrathin Silicon Oxide Film for Enhanced Performance and Reliability of Metal-Induced Laterally Crystallized Thin-Film Transistors Using Silicon Nitride as a Gate Dielectric

In this work, we successfully fabricated high performance and excellent reliability of metal-induced laterally crystallized (MILC) polycrystalline-silicon thin-film transistors (poly-Si TFTs) with various surface treatments. The MILC poly-Si TFTs using silicon nitride as a gate dielectric shows high grain-boundary and interface trap-density with the MILC poly-Si film. Therefore, several surface treatment techniques, including oxidizing silicon surface with HNO3, H2SO4, and HCl, as well as N2O plasma treatment, were investigated. Comparing the characteristics of the proposed MILC poly-Si TFTs, the N2O plasma treated was the most effective, showing superior electrical performance and reliability to the other surface treatment methods. The role of the N2O plasma is to insert nitrogen into the poly-Si surface, which causes a relaxation and passivation of the trap states by producing Si≡N strong bonds, while the surface treatments using acids simply oxidize Si atoms.

Abnormal Output Characteristics of p-Type Low Temperature Polycrystalline Silicon Thin Film Transistor Fabricated on Polyimide Substrate

We report on an abnormal output characteristics in p-type low temperature polycrystalline silicon thin-film transistors fabricated on polyimide (PI); negative differential conductance behavior is often observed in saturation region of drain current from large width devices. To understand such abnormal output characteristics, device dimension dependence was studied in a systematic way. As a result, we found that enhanced self-heating is mainly responsible originating from the poor thermal conductivity of PI substrate. A related degradation model is also proposed.

A 550-PPI LCD using 1.5 µm channel width LTPS TFTs with low frame rate driving

A 550 PPI low-temperature polycrystalline silicon thin-film transistor liquid-crystal display has been developed. Shrinkage of the channel width of pixel thin-film transistor together with thinner insulator for the storage capacitor allows high display quality in terms of vertical cross-talk and flicker. Thirty hertz frame rate driving is implemented to offer low power while keeping high display quality.

Poly‐Si TFTs with bottom‐gate structure using excimer laser crystallisation for AMOLED displays

An n-type polycrystalline silicon thin-film transistor (poly-Si TFT) with a bottom-gate structure using excimer laser annealing (ELA) for active matrix organic light-emitting diode displays is proposed. A problem with bottom-gate poly-Si TFTs (BGPs) using ELA, namely, the disconnection of poly-Si at the boundary of the gate metal during the ELA crystallisation, was solved by developing a novel process to control the slope of the gate metal. We realised ELA BGPs with pure-Mo gate having a thickness of more than 150 nm. The BGPs have better breakdown voltage characteristics compared with the conventional top-gate poly-Si TFTs because of its flat channel region and homogeneous electric field distribution in the gate insulator.

Abnormal Threshold Voltage Shifts in P-Channel Low-Temperature Polycrystalline Silicon Thin Film Transistors Under Negative Bias Temperature Stress.

In this research, we have investigated the instability of P-channel low-temperature polycrystalline silicon (poly-Si) thin-film transistors (LTPS TFTs) with double-layer SiO2/SiNx dielectrics. A negative gate bias temperature instability (NBTI) stress was applied and a turn-around behavior phenomenon was observed in the Threshold Voltage Shift (Vth). A positive threshold voltage shift occurs in the first stage, resulting from the negative charge trapping at the SiNx/SiO2 dielectric interface being dominant over the positive charge trapping at dielectric/Poly-Si interface. Following a stress time of 7000 s, the Vth switches to the negative voltage direction, which is "turn-around" behavior. In the second stage, the Vth moves from -1.63 V to -2 V, overwhelming the NBTI effect that results in the trapping of positive charges at the dielectric/Poly-Si interface states and generating grain-boundary trap states and oxide traps.

Deep Analysis of the Geometric Component in Charge Pumping of Polycrystalline Silicon Thin-Film Transistors

In this paper, we model the geometric component in a charge pumping (CP) technique of polycrystalline silicon thin-film transistors (poly-Si TFTs). This model is based on both remaining carrier types when the device transits from accumulation to inversion and vice versa. Therefore, it depends on gate length ( $L$ ) and width ( $W$ ) as well as on gate signal rise ( $t_{\!f}$ ) and fall time ( $t_{\!f}$ ). The proposed model shows good agreement with the experimental data. We have shown that the geometric component due to the remaining carriers, when poly-Si TFT transits from inversion to accumulation, is very small compared with that due to the transition from accumulation to inversion. Consequently, a new analytic CP model, depending on gate width, is developed for n-channel poly-Si TFT.

Effects of Channel Width on High-Frequency Characteristics of Trigate Poly-Si Thin-Film Transistors Fabricated by Microwave Annealing

In this paper, the high-frequency performance of trigate polycrystalline silicon thin-film transistors (poly-Si TFTs) is analyzed using low-temperature microwave annealing. The variation of the cutoff frequency and the maximum oscillation frequency with the width of the channel wire is investigated. A poly-Si TFT with a short channel and a narrow channel wire, annealed using microwave, has a high driving current, a good gate controllability, and a better high-frequency performance than one that annealed by rapid thermal annealing.

Compressive Stressed P-Channel Polycrystalline-Silicon Thin-Film Transistors for High Field-Effect Mobility

A compressively stressed polycrystalline-silicon (poly-Si) thin-film transistor (TFT) was successfully demonstrated on a tensile stressed glass substrate. The layer of a-Si:H/bare glass was annealed for 45 h with a sharp annealing and a slow cooled condition in order to form compressive strain on the a-Si:H film. Then, the a-Si:H was crystallized by NiSi <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> seed-induced lateral crystallization having (110) preferred texture, and the top-gated TFT was fabricated. The electrical properties were excellent comparing with the strain-free poly-Si TFT, and especially the field-effect mobility increased 9.3 times higher.

Anomalous Mobility Improvement in Ultra-Low-Temperature Polycrystalline-Silicon Thin-Film Transistors on Flexible Substrate after Laser Lift-Off Process

This work investigates an improvement in anomalous mobility in high-performance ultra-low-temperature polycrystalline-silicon (ULTPS) thin-film transistors (TFTs) on flexible substrate after laser lift-off process. The experiment results reveal that the improvement was observed in p-type TFTs but not observed in n-type ones. It was contributed to the boron atom has more kinetic energy than phosphorous one during laser lift-off process. Consequently, the effect of slight boron movement is to reduce the effective p-TFT channel length.Electronic devices fabricated on flexible substrates have drawn a lot of attention to recent researches in these years. Transistors on flexible substrates were the hearts of flexible technologies. Many literatures reported the implementing methods including carbon-nano-tubes transistors, amorphous silicon TFTs, amorphous IGZO TFTs, and etc.. Some of them suffered from either high temperature process or poor transistor characteristics. And the most important, some of them suffered from single polarity transistors, such only n-type transistors. A very attractive technology for flexible electronics was using ULTPS TFTs fabricated direct on flexible substrate on carrier glass [1]. It could not only realize large-size manufacturing process but also is compatible with current CMOS LTPS TFTs circuits. Since the ULTPS TFTs on flexible substrates needs to be lift-off from carrier glass, the electrical characteristics between before and after lift-off process should be studied. However, there were lacks of study of anomalous mobility improvement in p-channel ULTPS TFTs after laser lift-off process. In this experiment, the complementary ULTPS TFTs, i.e. n- and p- channel devices, were both fabricated on flexible material coated on carrier glass then lift-off by laser irradiation. The brief fabrication process was as followings. First, the carrier glass was coated by a layer of polyimide film. After curing, the complementary TFTs were fabricated under ultra-low temperature process by fine tune the recipes. Finally, to implement flexible electronic applications, the ULTPS TFTs were lift-off from the carrier glass by virtue of excimer laser irradiation. The laser irradiation energy densities were varied to investigate the lift-off process effects on the electrical performance of ULTPS TFTs, as shown in Fig1(a)-(c). One sample, named high-energy laser lift-off (HELLO), was irradiated at 320 mJ/cm2. The other sample, named low-energy laser lift off (LELLO), was irradiated at 300 mJ/cm2. And the device dimension was W/L=20um/4.5um for both n- and p- channel TFTs. As fabricated, the HELLO TFTs have been demonstrated the field-effect electron and hole mobility of 82 and 85 cm2/V-s, respectively, while the corresponding characteristics were 78 and 86 cm2/V-s for the LELLO TFTs. Both of them had the similar performance on carrier glass. After laser lift-off process, it was observed that the electron mobility were 81 and 77 cm2/V-s for HELLO and LELLO devices, accordingly. The hole mobility for LELLO TFTs was 88 cm2/V-s. In the contrast, that for HELLO TFTs was improved to 92 cm2/V-s. It could be seen that the electron mobility was not improved for both HELLO and LELLO devices. And no improvement in hole mobility was observed in LELLO devices, but on the contrary an anomalous hole mobility improvement was found in HELLO devices. In the meanwhile, no significant changes were observed in the other electrical parameters, such as threshold voltage and subthreshold swing[2]. The anomalous field-effect hole mobility improvement may be resulted from the reduction of interface trap density state and the shrinkage of channel. Since the subthreshold swing reflected the interface trap density state between gate insulator and channel and no changes were found, that interpreted that the interesting improvement was not caused by the reduction of interface trap density. On the other hand, since only the HELLO p-channel exhibited the interesting anomalous improvement, it is believed that the boron atom is lighter than phosphorous and diffused during laser lift-off process. Therefore, the boron diffusion occurred only when the laser lift-off energy density. Consequently, the source and drain dopants, namely boron, were slight diffusing into the channel to reduce effective channel length. In conclusion, we investigated the anomalous improvement in p-channel ULTPS TFTs after the high-energy laser-lift-off process. The hole mobility was improved from 85cm2/V-s to 92cm2/V-s. It is believed that these anomalous phenomena may be contributed to boron diffusion caused reduction of channel length. The ULTSP TFTs are promising to future flexible electronic circuits. Reference [1] ISDRS 2009, December 9-11, 2009, College Park, MD, USA [2] IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 11, NOVEMBER 2010 Figure 1

Impact of repeated uniaxial mechanical strain on p-type flexible polycrystalline thin film transistors

This letter investigates the effect of repeated bending of flexible p-channel low-temperature polycrystalline–silicon thin-film transistors employing an ultra-low-temperature process (&amp;lt;673 K). Experimental results reveal that interface state density (Nit) and grain boundary trap density (Ntrap) after 10 000 width-axis tensile strain bending iterations are more pronounced than after equivalent width-axis compressive strain bending. Extracted interface and grain boundary traps both increase, which elevate trap assisted leakage. Furthermore, the bending distorts the Si–Si bonds in the polycrystalline silicon (Poly-Si) film, which causes more significant negative bias temperature instability (NBTI) degradation because strain-induced weak Si–Si bonds can react with dissociated H during NBTI stress.

Using dual plasma treatment to improve electrical characteristics and reduce flicker noise of high-κ HfO2 LTPS-TFTs

This study demonstrated the application of a dual plasma treatment to low-temperature polycrystalline-silicon thin-film transistors (LTPS-TFTs) comprising a self-aligned phosphorus implantation source and drain, high-κ HfO2 gate dielectric, and aluminum metal gate. The dual plasma treatment involves a pre-deposition CF4 plasma treatment at a high-κ/poly-Si interface and post-deposition N2 plasma treatment at a high-κ HfO2 gate dielectric; this treatment enables reducing the interface-trap-state defects at the high-κ/poly-Si interface, grain boundary traps in the poly-Si channel film, and oxygen vacancy Vo in the high-κ HfO2 gate dielectric. Thus, LTPS-TFTs with dual plasma treatment demonstrate excellent electrical characteristics such as threshold voltage, subthreshold swing, transconductance, driving current, and on/off current ratio. Flicker noise, also referred to as 1/f noise, caused by fluctuations of carriers transported in the grain boundary and the trapped carriers per unit oxide volume (Nt) can be suppressed. Therefore, high performance LTPS-TFTs subjected to dual plasma treatment can be appropriately applied to active matrix liquid phase-crystal display on system-on-panel technology.

High-Frequency Performance of Trigate Poly-Si Thin-Film Transistors by Microwave Annealing

This letter investigates the high-frequency performance of trigate polycrystalline silicon thin-film transistors (poly-Si TFTs) using low temperature microwave annealing (MWA). MWA exhibits sufficient dopant activation efficiency, good short channel effect control, and a higher maximum oscillation frequency (f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> ) of poly-Si TFTs than does rapid thermal annealing. In addition, MWA can fabricate nanoscale devices. Poly-Si TFTs with short channel annealed by microwave reveals better high-frequency performance and switching characteristics.

High Efficiency Driver for AMOLED with Compensation

A new proposed compensation driver circuit of flat-panel display (FPD) based on organic light emitting diodes (OLEDs) and on poly-crystalline silicon thin-film transistors (poly-Si TFTs) is presented. This driver circuit is developed for an active-matrix organic light-emitting-diode (AMOLED) display and its efficiency is verified compared with the conventional configuration with 2 TFTs. According to results, this circuit is suitable to achieve acceptable level for power consumption, high contrast, maximum gray levels, and better brightness. And, to show this, a stable driving scheme is developed for circuit with much compensation such as against the data degradation, the threshold voltage dispersions of TFT drive, and suppression of TFT leakage current effect.

Block-Oxide Structure in Polycrystalline Silicon Thin-Film Transistor With Source/Drain Tie and Additional Polycrystalline Silicon Body for Analog Applications

In this paper, we for the first time demonstrate the analog performance of a block-oxide structure in polycrystalline silicon thin-film transistor with source/drain-tie and additional poly-Si body (BO-SDT-APSB TFT) experimentally and compared with the similar device with zero block-oxide structure (SDT-APSB TFT). The block-oxide in BOSDT-SDT-APSB TFT is fabricated to reduce the drain-induced barrier lowering and channel-length modulation. The source-drain tie and additional poly-silicon body region are fabricated in both devices to improve the device performance and reduce the self-heating effect. Experimental results show that the block-oxide structure can offer enhanced gate controllability over the channel, and the transconductance ( g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> ) of the BO-SDT-APSB TFT is therefore improved. In addition, although a higher drain conductance ( g d), implying a lower output resistance r o, is observed for a BO-SDT-APSB TFT, the enhanced gm still helps to achieve the desired intrinsic voltage gain ( A <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">v</sub> = g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> /g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</sub> ) behavior.

Significant Reduction of Dynamic Negative Bias Stress-Induced Degradation in Bridged-Grain Poly-Si TFTs

The device degradation of bridged-grain (BG) polycrystalline silicon thin-film transistors under dynamic negative bias stress (NBS) is investigated for the first time. By employing a BG structure in the active channel, dynamic NBS-induced hot carrier degradation could be significantly reduced from -99.9% to -2.4% (10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> s dynamic NBS), which is attributed to a sharing of the lateral electric field across the multiple p-n junctions inherent in the structure. The nonequilibrium junction degradation model is employed and developed, incorporated with TCAD simulations.

Thermal Stress Effects on the Electrical Properties of p-Channel Polycrystalline-Silicon Thin-Film Transistors Fabricated via Metal-Induced Lateral Crystallization

We developed a method to compact the glass sheets of a flat-panel displays that use metal-induced laterally crystallized (MILC) polycrystalline-silicon (poly-Si) thin-film transistors (TFTs), and the effects of thermal stress on the fabricated devices were compared against those of a bare-glass device. The glass substrate was exposed to a temperature of 650 °C for 40 h in order to suppress the glass shrinkage to 0.01 ppm, which suitable for a MILC poly-Si TFT process. The compressive strain that originates from glass shrinkage generally increases the size of the micro-cracks and the vacancies, and as a result, most of the electrical parameters of a bare glass device (such as the on-current, off-current, field-effect mobility, subthreshold slope, and threshold voltage) had a higher level of degradation than those of the device with the compacted glass. The increase in the on-current and the field-effect hole mobility under the compressive strain for poly-Si TFTs showed a similar behavior to that of single-crystalline-silicon (c-Si) TFTs under compressive strain. However, the increase in the off-current was the converse of that of strained c-Si TFT.

A Three-Transistor Pixel Circuit to Compensate for Threshold Voltage Variations of LTPS TFTs for AMOLED Displays

This work presents a new pixel circuit adopting low-temperature polycrystalline-silicon thin-film transistors (LTPS TFTs) for active-matrix organic light-emitting diode (AMOLED) displays. The proposed pixel circuit can compensate for the threshold voltage variations of the LTPS TFTs with a simple structure. Simulated results demonstrate that the OLED currents over the entire data voltage range are uniform for $\pm {\hbox{0.5}}~{\hbox{V}}$ variations in the threshold voltage of the driving TFT, unlike in a conventional circuit. Furthermore, the relative current error rates for parasitic loads in the 1280 $\times$ 720 resolution AMOLED display are less than 6%.

Approximate analytical channel potential model of poly-Si thin film transistors operated in the strong inversion region under the high gate and low drain biases

An approximate analytical channel potential model of polycrystalline silicon thin film transistors operated in the strong inversion region under the high gate and low drain biases is proposed. Thus, the linear relationship between the channel potential and the drain voltage is derived in the strong inversion region under the above bias condition when the polysilicon layer is ultrathin. This model agrees with the two-dimensional-device simulation results under different gate voltages, different drain voltages and different channel lengths. By comparing the relative errors between the model and the simulation results, it presents that this model is more suitable under the higher gate voltage Vg or the lower drain voltage Vd, regardless of the channel length. And this approximate analytical model is helpful in solving the two- dimensional-device problem by one-dimensional Poisson's equation since the drain bias is taken into account in the channel potential.

A novel current-biased voltage-programmed pixel circuit with low temperature polycrystalline silicon thin film transistors for AMOLED

A novel current-biased voltage-programmed pixel circuit with low temperature polycrystalline silicon thin film transistors for AMOLED

Selectively Nucleated Lateral Crystallization for a Large Single-Grained Pb(Zr,Ti)O3 on Polycrystalline-Silicon Thin-Film Transistors for System-On-Glass Applications

ABSTRACTA single-grained Pb(Zr,Ti)O3 (PZT) was successfully grown for the gate dielectric of polycrystalline-silicon (poly-Si) thin-film transistor (TFT). The total structure was MoW/PZT/HfO2/poly-Si/glass. The giant single-grained PZT was obtained by controlling the artificial nucleation formed by Pt dots in a desirable location and enlarging the nucleated seed until it covers the poly-Si channel. The single-grained diameter size was 40 μm with a (100) dominated texture. The poly-Si memory device with single-grained PZT showed an excellent ferroelectric, electrical and reliability properties comparing with poly-Si memory device with poly-grained PZT. Moreover, eliminating the grain boundary in PZT film showed the fatigue and retention characteristics with only 1.1 % after 1013 cycles and 22 % after 1 month, respectively.