Polycrystalline Silicon Thin-film Transistors Research Articles

Binary-Synaptic Plasticity in Ambipolar Ni-Silicide Schottky Barrier Poly-Si Thin Film Transistors Using Chitosan Electric Double Layer.

We propose an ambipolar chitosan synaptic transistor that effectively responds to binary neuroplasticity. We fabricated the synaptic transistors by applying a chitosan electric double layer (EDL) to the gate insulator of the excimer laser annealed polycrystalline silicon (poly-Si) thin-film transistor (TFT) with Ni-silicide (NiSi) Schottky-barrier source/drain (S/D) junction. The undoped poly-Si channel and the NiSi S/D contact allowed conduction by electrons and holes, resulting in artificial synaptic behavior in both p-type and n-type regions. A slow polarization reaction by the mobile ions such as anions (CH3COO− and OH−) and cations (H+) in the chitosan EDL induced hysteresis window in the transfer characteristics of the ambipolar TFTs. We demonstrated the excitatory post-synaptic current modulations and stable conductance modulation through repetitive potentiation and depression pulse. We expect the proposed ambipolar chitosan synaptic transistor that responds effectively to both positive and negative stimulation signals to provide more complex information process versatility for bio-inspired neuromorphic computing systems.

Electrical-performance and reliability improvement of flexible low-temperature polycrystalline silicon thin-film transistors via post-annealing process

We investigated the improvement methods of the electrical characteristics and reliability of flexible low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) by optimizing the annealing process. We investigated the effect of annealing on the device properties via electrical measurement and density-of-state (DOS) analysis. The annealing temperature should be reduced for flexible LTPS TFTs compared to rigid devices because the range of the thermal stability of flexible substrate is narrower than that of the glass substrate. As the activation annealing temperature (T a) decreased, the threshold voltage and field-effect mobility (μ FE) decreased, and the subthreshold swing (SS) increased. When the post-annealing temperature (T pa) decreased, μ FE increased, and the changes in the other parameters were negligible. The DOS decreased with an increase in T a and a reduction in T pa. These results originated from ineffective dopant activation and defect curing due to the lower T a and the enhanced hydrogen defect passivation at the lower T pa. Therefore, flexible LTPS TFTs with reduced T a values exhibited similar μ FE values and lower SS values when the post-annealing process was omitted. Furthermore, removing the post-annealing process improved the reliability of the flexible LTPS TFTs with reduced T a values under electrical stress. According to a hot-carrier instability analysis, defect passivation by hydrogen was more stable than defect curing with a higher T a. Consequently, although T a was low for flexible LTPS TFTs, the electrical performance and reliability could be improved by optimizing the post-annealing process.

Modeling of High-Current Polycrystalline Silicon Thin Film Transistors by Incorporating Buried Electrode

For display applications, high current and large on/off current ratio are pursued for driving and switching transistors. In this article, a thin film transistor (TFT) device incorporating a buried electrode is proposed, which enables increasing the driving current by reducing the channel length, with the channel length only at the drain side. This lateral short-channel TFT enables increasing the on-current while maintaining the field effect mobility, in comparison to our experimental short-channel vertical TFT structure. Another advantage of the proposed structure lies in the suppression of the Schottky barrier at the source and drain contacts when using high-work-function source/drain contacts for an N-type TFT, with an increased on/off current ratio reaching approximately 106. The suppression of Schottky barrier at the source/drain has been verified by the contact resistance measurements. Even though high driving current is obtained, the off-current is still high due to the weakened electric field at the source/drain sides and needs to be further optimized.

Simplified EKV model parameter extraction in polysilicon MOSFETs

We present an easy but effective method to extract the four parameters of the simplified Enz–Krummenacher–Vittoz (sEKV) MOSFET model. The procedure, which is based on direct lateral optimization, is tested using measurements from experimental polycrystalline silicon Thin Film Transistors (TFTs) of various channel lengths and widths. We demonstrate that this basic MOSFET model is able to reasonably describe the saturation transfer characteristics of these polysilicon TFTs. Furthermore, we evaluate the computational adeptness for extracting the four sEKV parameters of the lateral optimization fitting procedure as compared to the more traditional vertical optimization one.

Improvement of the low gray-level expression using hybrid pulse width modulation and pulse amplitude modulation driving method for a micro light-emitting diode pixel circuit

A novel hybrid pulse width modulation (PWM) and pulse amplitude modulation (PAM) (HPP) driving method is proposed for improving the low gray-level expression of a micro light-emitting diode (µLED) display. At the high and middle gray-levels, PWM is adopted in order to suppress the wavelength shift of µLEDs. At the low gray-level, PAM is applied when the emission time and current of µLEDs simultaneously decrease. The HPP driving method is simulated by using a simplified p-type low-temperature polycrystalline silicon (LTPS) thin-film transistor (TFT)-based µLED pixel circuit. HPP driving exhibits stable PWM and PAM operations. Furthermore, HPP driving guarantees a data voltage range approximately 14 times larger than PWM driving, thus resulting in a robust operation with a maximum error rate of 3.83% under data signal distortion. Consequently, the µLED pixel circuit adopting HPP driving improves the low gray-level expression and demonstrates a robust circuit operation.

14‐4: Enhanced Low Temperature Polycrystalline Silicon Thin‐Film Transistor Device Structure by Doping at Channel Edge

In this study, we propose a new low temperature polycrystalline silicon thin film transistor structure with good driving and reliability characteristics. The structure was proposed through TCAD simulation and verified through several simulation models. Thereafter, actual devices were manufactured to prove that characteristics were improved.

P‐32: Investigation on Mechanism of Illumination Mura in AMOLED Display with LTPS‐TFT Backplane after Long Term Localized Illumination

Low‐temperature polycrystalline silicon (LTPS) thin film transistors have been widely used in AMOLED display applications due to the high mobility and the capability of realizing peripheral and active matrix circuits on glass. Though LTPS TFTs exhibited relatively good electrical performance and stability, illumination Mura on AMOLED display with LTPS backplane could be observed by naked eye after several hours’ illumination on localized display area. The Mura boundary separates the areas with and without illumination when the AMOLED display is lighted on without pattern. The electrical instability of LTPS TFT was proved to be the main underlying cause. The DTFT threshold voltage compensation effect and SS variation in 7T1C pixel circuit has certain relationship with the illumination Mura detail.

Enhancing Reliability and 2 mm-Axial Mechanical Bending Endurance by Gate Insulator Improvements in Flexible Polycrystalline Silicon TFTs

In this study, the electrical performance and bending stress endurance of flexible low-temperature polycrystalline silicon thin film transistors (LTPS TFTs) are enhanced by increasing the helium concentration (1500 sccm) during gate insulator (GI) manufacture to create a high-quality GI device. Experimental results confirm that the subthreshold swing (S.S.) and mobility of these new &#x201C;high-flow&#x201D; devices are better than those with a lower helium concentration, which we term &#x201C;low-flow&#x201D; devices. The flow of helium gas is increased to achieve a better-quality oxide layer. The energy-dispersive X-ray spectroscopy (EDS) line data show a clear enhancement in oxygen content in the devices under this helium gas process. After mechanical compression and tensile bending stresses of 100000 iterations in the channel width-axis direction, perpendicular to the channel, with bending at <inline-formula> <tex-math notation="LaTeX">${R} = {2}$ </tex-math></inline-formula> mm, the modified GI devices with their more Si-O bond content exhibit less stress damage in the GI layer than do low-flow devices. As a result, this new manufacturing condition can effectively reduce the electrical degradation after negative-bias temperature stress (NBTS), and improve the overall electrical performance.

Strain distribution and electrical characteristics of flexible low-temperature polysilicon thin film transistors under biaxial bending

This paper investigates the strain distribution of flexible p-channel low temperature polycrystalline silicon thin film transistors under biaxial bending. The strain distribution of LTPS TFTs under different bending conditions is analysed by finite element analysis. \U0001d6c6r and \U0001d6c6θ are essentially equal and constant within the load ring. The finite element analysis shows that when the biaxial bending strain condition is 2.5%, the strain distribution is mainly concentrated at the contact angle between the electrode and the oxide layer. This strain is significantly greater than the overall strain of the device, which is the main reason for the bending performance of the device. We found that under biaxial bending, the threshold voltage shifts towards the negative axis as the biaxial strain increases. Within this strain range, these electrical properties are evident under biaxial strain conditions. Comparing theoretical threshold voltage shifts based on energy band changes with experimental results under biaxial strain, it was found that changes in trap density should also contribute to the threshold voltage shift.

Abnormal Two-Stage Degradation on P-Type Low-Temperature Polycrystalline-Silicon Thin-Film Transistor Under Hot Carrier Conditions

In this study, an abnormal two-stage degradation of low-temperature polycrystalline-silicon (LTPS) thin-film transistors (TFTs) on a polyimide flexible substrate after hot carrier stress was investigated. The degradation mechanism was divided into two stages. In the first stage, the increases in capacitance in the off region and transconductance are caused by impact ionization induced electron trapping into the gate insulator (GI) at the drain edge. Furthermore, the threshold voltage (<inline-formula> <tex-math notation="LaTeX">$\text{V}_{\text {th}}$ </tex-math></inline-formula>) shift in the positive direction is caused by electrons flowing back to the source side and trapping into the buffer that induces source barrier lowing. The second stage of degradation, including a <inline-formula> <tex-math notation="LaTeX">$\text{V}_{\text {th}}$ </tex-math></inline-formula> shift in the negative direction and a decrease in the transconductance is caused by Joule heating induced negative bias temperature instability (NBTI). Furthermore, NBTI hardly occurs behind the pinch off in the channel and fixed oxide charge does not compensate the trapped electron at drain side which is induced in the first stage.

Suppressing Drain-Induced Barrier Lowering and Kink Effect in Low-Temperature Poly-Si TFTs Using a Partitioned Light Shield

Anomalous drain-induced barrier lowering (DIBL) is observed in n-type low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs) with a full light shield (LS) structure. Drain current versus gate voltage curves exhibit a threshold voltage (V_TH) shift and hump effect as the drain bias increases, and demonstrate the unsaturated output property. Because of the inherent grain boundary and grain protrusion of LTPS TFTs, considerable impact ionization occurs, thus generating electron&#x2013;hole pairs when operated at high current, leading to a floating body effect, that confers the occurrence of the kink effect. However, the unsaturated current characteristic is induced by the LS because of its coupling potential of the LS. Therefore, partitioned LS structures are proposed to further improve the DIBL and weak the kink effect.

Improvement of Strained Negative Bias Temperature Instability in Flexible LTPS TFTs by a Stress-Release Design

In this study, the negative bias temperature instability (NBTI) under mechanical strain conditions of low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs) with a stress-release structure was investigated. With both electrical and mechanical stresses simultaneously applied, more significant degradation behaviors will be observed in standard TFT devices because mechanical stress makes it easier to generate strain in Si–H bonds, thus benefiting the process of electrochemical reaction. By employing a stress-release shape in the poly channel, mechanical stress, which mainly accumulates at the width edge of the poly-Si/SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> interface, is moved away from the main channel; thus, fewer strained Si–H bonds can participate in the electrochemical reaction compared to the standard structure. Therefore, the degradation of devices under strained NBTI is effectively mitigated, such that the reliability of the devices is enhanced. These observations were obtained using electrical characteristics and extraction of the trap state distribution.

Demonstration of synaptic characteristics of polycrystalline-silicon ferroelectric thin-film transistor for application of neuromorphic computing

In this work, the synaptic characteristics together with 5 bits (32 states) operation based on polycrystalline-silicon (poly-Si) ferroelectric thin-film transistor (FeTFT) with HfZrO x gate dielectric are demonstrated for the first time. A 1.2 V threshold voltage shift of memory window is obtained. The impacts of pulse time on the potentiation and depression states are studied by a modulation scheme with incremental pulse voltages. The potentiation and depression rates of the conductance (G d) states of FeTFTs are found to be asymmetric and become more severe when increasing the pulse time. In order to realize high recognition rate and accuracy of neuromorphic computing, low asymmetric nonlinearity of potentiation () and depression () of poly-Si FeTFTs can be achieved with the reduction of operation voltage. Low asymmetry = 0.71 and high G d ratio ∼40 of FeTFTs are obtained based on the small pulse time of 50 ns and low average potentiation/depression voltages of 2.63/–2.69 V. When the pulse time is increased from 50 to 150 ns, the average potentiation/depression voltages can be further reduced to ∼1.59/–1.69 V for low asymmetry = 0.25 due to the enhanced G d potentiation and depression rates, and the G d ratio is also reduced to 9.96 with the reduction of potentiation/depression voltages. The small pulse time and potentiation/depression voltages of FeTFTs are responsible for the polarization switching of the ferroelectric layer following the minor operation-loop. Compared to the depression state, it leads to more stable retention and endurance behavior of the potentiation state due to the different depolarization electric fields.

Shear-Force Sensor With Point-Symmetric Electrodes Driven by LTPS TFT Active Matrix Backplane

In this study, we successfully demonstrated a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$700 ~\mu \text{m}$ </tex-math></inline-formula> thick shear-force sensor with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$60\times60$ </tex-math></inline-formula> high resolution array by introducing a combination of an originally developed pressure-sensing elastomer and a newly proposed taxel (tactile pixel) structure with four point-symmetric electrodes. When shear forces are applied to the sensor substrate in several directions by lifting a weight, four sets of resistances between the electrodes are read through low-temperature polycrystalline-silicon (LTPS) thin-film transistors (TFTs) in each taxel and clear outputs corresponding to that direction can be confirmed. Furthermore, as a result of evaluating the object recognition performance of the tactile sensor by using jigs with engraved small dimples, it was confirmed that the recognized minimum size of the shape was 1.5 mm, which suggests that the spatial resolution of this sensor is superior to the human hand perception ability. Because this sensor is ultra-thin, not bulky, and potentially applicable to flexible substrates, it is quite promising as a sensor that can be mounted on the fingertip of a robot hand with multiple functions.

Investigation on operation robustness of p-type low-temperature polycrystalline silicon thin-film transistor-based micro light-emitting diode pixel circuit using pulse width modulation under component fluctuation

In this study, we have investigated the operation robustness of a p-type low-temperature polycrystalline silicon (LTPS) thin-film transistor (TFT)-based micro light-emitting diode (µLED) pixel circuit adopting pulse width modulation (PWM) under circuit component fluctuations. The wavelength shift of µLEDs, depending on the current density, was suppressed by implementing PWM. The PWM pixel circuit controlled the emission time with constant µLED current in the simulated and measured results. In addition, the wavelength shift was suppressed below 0.48% within the 10-bit grayscale range. Furthermore, the component tolerance of the pixel circuit was investigated by simulating the error rate of µLED emission time with varying threshold voltage, mobility, subthreshold swing, and capacitance. The pixel circuit exhibited a robust operation with a maximum error rate of 4.0% under a component fluctuation of ±10%. Consequently, the µLED pixel circuit adopting PWM suppressed the wavelength shift of µLEDs and demonstrated robust circuit operation under component fluctuation.

Novel channel edge doping for hump reduction in LTPS TFTs

We proposed a new channel edge doping (CED) technique for hump reduction in n-type low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) and validated it through experiments and technology computer-aided design (TCAD) simulations. The TCAD simulations indicate that the hump effect in LTPS TFTs is due to the high electron (e−) concentration (∼1016 cm−3) induced by an enhanced electric field (e-field) at the channel edge region along the width direction. In order to reduce the hump effect, we focused on decreasing the e− concentration at the channel edge. The CED process led to the selective control of the e− concentration at the channel edge. The decrease in the maximum e− concentration from 3.4 × 1016 to 2.9 × 1014 cm−3 at the channel edge using CED led to an effective reduction in the hump characteristic of LTPS TFTs. Furthermore, the CED process does not require any additional masks and is highly effective in hump reduction, rendering it beneficial for manufacturing active-matrix organic light-emitting diode displays.

A Low Power and IR Drop Compensable AMOLED Pixel Circuit Based on Low-Temperature Poly-Si and Oxide (LTPO) TFTs Hybrid Technology

In this paper, an AMOLED pixel circuit based on low-temperature poly-crystalline silicon and oxide (LTPO) thin-film transistors (TFTs) hybrid technology is proposed, which features only two transistors in a serial connection with OLED. The power supply can thus be reduced by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$25{\sim }30$ </tex-math></inline-formula> % in the “Always-on-Display” (AOD) mode compared with the earlier LTPO pixel circuits which usually have three transistors in the current path and need a higher supply voltage. Furthermore, in addition to a strong suppressing ability to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{V}_{\mathrm{ th}}$ </tex-math></inline-formula> variations/shift, the proposed pixel circuit has an excellent compensation ability for current-resistance voltage drops (i.e., IR drop), which is also superior to the earlier LTPO ones where the IR drop has to be compensated externally. Therefore, the proposed LTPO pixel circuit is able to provide AMOLED displays with lower power consumption and higher display performance than the earlier ones.

AM Mini-LED Backlight Driving Circuit Using PWM Method With Power-Saving Mechanism

This paper proposes a mini-light-emitting diode (mini-LED) driving circuit that is driven by pulse width modulation (PWM) for the backlights of active-matrix (AM) liquid crystal displays (LCDs). The proposed circuit compensates for threshold voltage (V_TH) variations of low-temperature poly-crystalline silicon thin-film transistors (LTPS TFTs) and the current-resistance (I-R) rise in VSS lines to supply a stable driving current. Operating the mini-LED at the high luminous efficacy by the PWM driving method and setting only the driving TFT on the path of the driving current reduce the power consumption of the backlight. Based on a 2.89-inch LCD panel with an AMLED <inline-formula> <tex-math notation="LaTeX">$48\times48$ </tex-math></inline-formula> backlit module, the TFTs are fabricated, measured, and fitted. Simulation results show that the relative current error rates are all below 4.67&#x0025; when the V_TH of the driving TFT varies by &#x00B1;0.3 V and the VSS rises by 0.5 V. The voltage across VDD and VSS of the proposed circuit is 4.5 V lower than that of the 6T1C compensating driving circuit, so the power consumption of the circuit is at least 27.05&#x0025; lower. Therefore, the proposed driving circuit is well suitable to use in mini-LED backlit LCDs.

A Novel Gate Driver Working Under Depletion Mode Oxide TFTs Using Low-Temperature Poly-Si Oxide TFTs

We report a novel gate driver integrated by low-temperature poly-Si oxide (LTPO) thin-film transistors (TFTs). The proposed gate driver consists of four p-type low-temperature polycrystalline silicon (LTPS) TFTs and two n-type amorphous indium gallium zinc oxide (a-IGZO) TFTs. Dual-gate (DG) a-IGZO TFTs, having high drain currents and excellent reliability, are utilized. The fabricated gate driver operates with a pulse width of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1~\mu \text{s}$ </tex-math></inline-formula> corresponding to operating speed of 500 kHz at voltage swing of 15 V. Also, the proposed LTPO gate driver works well without malfunction with strong depletion mode a-IGZO TFTs having threshold voltage of −5.5 V. It is exhibited that the ripples, which appear when a-IGZO TFTs have negative threshold voltage, are perfectly removed by regulating two input DC signals.

Flexible High-Temperature Polycrystalline Silicon Thin Film Transistor on Metal Foil With S/D Doped by Diffusion

This article presents results on flexible high-temperature polycrystalline silicon (FHTPS) thin-film transistor (TFT) fabricated on metal foils. Metal foils eliminate processing temperature constraints which are rather stringent on flexible TFT devices fabricated on plastics and allow high-temperature post-crystallization annealing (PCA). The source/drain (S/D) area of the devices was doped by diffusion with a spin-coated solid source at high temperatures and this process also functioned as PCA to improve the quality of the active undoped area. Solid-phase crystallized TFTs with diffused S/D at 800 °C demonstrate saturation mobility ( μ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SAT</sub> ) of 103 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> / V·s, an I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> \scriptscriptstyle ON</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> \scriptscriptstyle OFF</sub> ratio of close to 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sup> , a subthreshold swing (SS) of 498 mV/dec, and a threshold voltage ( V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> ) of 4.9 V. Technology computer-aided design (TCAD) simulations reveal that parasitic resistance accounts for most of the performance variations of devices diffused at different temperatures when the devices are turned on, and defect density is dominant in the subthreshold and the off regimes. The performance of the fabricated devices suffered only slight changes after 10 000 cycles of bending with 7 mm radius showing their mechanical robustness.