Impacts of Vertically Stacked Monolithic 3D-IC Process on Characteristics of Underlying Thin-Film Transistor

William Cheng-Yu Ma,Yan-Shiuan Chang,Po-Jen Chen,Jhe-Wei Jhu,Ting-Hsuan Chang,Yan-Jia Huang

doi:10.1109/jeds.2020.3009350

William Cheng-Yu Ma, Yan-Shiuan Chang + Show 4 more

Open Access

https://doi.org/10.1109/jeds.2020.3009350

Copy DOI

Abstract

In this work, the high-performance junctionless-mode (JL) and low-power inversion-mode (IM) polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) with nanosheet channels (less than 10-nm in thickness) are vertically integrated in monolithic three-dimensional integrated circuit (3D-IC) structure. Both JL and IM TFTs can exhibit high on/off current ratio over 10 7 to demonstrate their performance. The JL TFT has much higher on-state current ~ 24 times than it of the IM TFT. And the IM-TFT has much lower SS ~ 0.104 V/decade and off-current ~ 0.04 times than them of the JL TFT. However, the fabrication of the top-devices (JL TFTs) would degrade the performance of underlying-devices (IM TFTs), resulting in the threshold voltage shift of the IM TFTs from 0.61 to 2.17 V, SS increase from 0.104 to 0.218 V/decade and on-state current degradation from 16 to 3 mA. In order to further understand the reasons, the IM TFT with top-device removal process is also fabricated, which exhibits a partial recovery in performance. The results indicate the presence and fabrication process of the top-device would lead to the defect generation in the underlying-device. The results provide a new consideration for monolithic 3D-IC manufacturing technology.

Highlights

Polycrystalline-Silicon thin-film transistors (TFTs) have been extensively studied for driving circuit of display panel, static random access memory (SRAM), dynamic random access memory, non-volatile memory, and threedimensional integrated circuit (3D-IC) [1]–[7]
The VTH of inversion mode (IM) TFT is defined as VG at ID = 10 nA x W/L due to the thinner channel film and lower Ion
The JL TFT has much higher Ion ∼ 400 mA than it of the IM TFT ∼ 16 μA due to the heavily doped poly-Si channel and thicker channel thickness, which is suitable as the high-performance devices

Summary

Introduction

Polycrystalline-Silicon (poly-Si) thin-film transistors (TFTs) have been extensively studied for driving circuit of display panel, static random access memory (SRAM), dynamic random access memory, non-volatile memory, and threedimensional integrated circuit (3D-IC) [1]–[7]. For the requirements of system-on-chip, high-performance devices and low-power devices need to be integrated in the same chip [8]–[10]. Low-power devices require low off-state leakage current, the on-state current would be lower. As for the high-performance characteristics of polySi TFT, junctionless-mode (JL) TFT is a good candidate because it can provide higher driving current due to the heavily doped poly-Si channel [11]–[15]. As for the low-power characteristics of poly-Si TFT, channel thickness thinning of conventional IM TFT is an effective manner to suppress the short-channel effect and leakage current [16]. The electrical characteristics of both JL and IM TFTs are strongly related to the channel film thickness that thinner channel film thickness leads to lower subthreshold swing (SS), off-state leakage current and on-state driving current [15], [16]. The JL TFT for high-performance applications and the IM TFT for

Methods

Results

Conclusion