Abstract
High-performance low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) have been developed for larger applications than flat panel displays (FPDs) such as three-dimensional integrated circuits (3D-ICs) and glass sheet computers. The crystallinity of poly-Si thin films has been the key factor determining TFTs’ performance. In this work, a void-defect location has been controlled by patterning amorphous silicon (a-Si) thin films with rectangular and square holes before crystallized by multiline continuous-wave laser beam to avoid the effect of void-defects on the TFTs’ performance. Instead of randomly appearing in the poly-Si thin films, void-defects were only observed at the backsides of the patterned holes. Interestingly, large crystal grains without void-defects were laterally crystallized at Si strips between holes. By observing the crystallinities of poly-Si thin film around the patterned holes, both the mechanism of the void formation and crystal growth based on temperature gradient was clarified.
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