Abstract
In this study, we investigate the transfer characteristics of low‐temperature polycrystalline silicon(LTPS) thin film transistors(TFTs) often show a “hump” in subthreshold region. This effect can be attributed to the presence of an enhanced electrical field at edges of the active layer. To reduce the hump effect which is one of the critical issues in ploy‐Si TFT, we focus on crowding of gate fringing field at channel edge and suggest a modified structure of channel edge. Using dry etching process, change the polysilicon layer at the edge of the channel from a steep profile to a slightly flat profile. And we confirmed that the severity of the hump effect is directly related to the edge profile of the polysilicon.
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