Influences of Grain Boundaries on Temperature Dependence of Device Characteristics and on Hot Carrier Effects in Low-Temperature Polycrystalline Silicon Thin Film Transistors Containing Large Grains

Abstract

The dependences of field-effect mobility, threshold voltage, and subthreshold slope on temperature for low-temperature polycrystalline silicon (LTPS) thin film transistors (TFTs) with large grains were investigated. It was shown that the temperature dependences of field-effect mobility and threshold voltage are affected by the temperature dependence of negatively charged grain-boundary-related interface traps near the surface of polycrystalline silicon, which is explained by considering that the degree of band bending at the surface when gate voltage is equal to threshold voltage decreases with increasing temperature. It was also shown that the behavior of a subthreshold slope can be explained using a term of the grain-boundary-related interface traps near the surface. Moreover, the effects of grain boundaries on hot-carrier generation and hot-carrier-induced degradation were investigated separately, and both processes were experimentally found to be affected by the grain boundaries.