Polycrystalline Silicon Nanowire Research Articles

A proposal and simulation analysis for a novel architecture of gate-all-around polycrystalline silicon nanowire field effect transistor

A proposal for a novel gate-all-around (GAA) polycrystalline silicon nanowire (poly-SiNW) field effect transistor (FET) is presented and discussed in this paper. The device architecture is based on the realization of poly-SiNW in a V-shaped cavity obtained by tetra methyl ammonium hydroxide (TMAH) etch of monocrystalline silicon (100). The device’s behavior is simulated using Silvaco commercial software, including the density of states (DOS) model described by the double exponential distribution of acceptor trap density within the gap. The electric field, potential, and free electron concentration are analyzed in different nanowire regions to investigate the device's performance. The results show good performance despite the high density of deep states in poly-SiNW. This can be explained by the strong electric field caused by the corner effect in the nanowire, which favors the ionization of the acceptor traps and increases the free electron concentration.

Polycrystalline silicon nanowire FET performance depending on density of states

Polycrystalline silicon nanowire FET performance depending on density of states

Polycrystalline Silicon Nanowire Field Effect Transistor Biosensors for SARS-CoV-2 Detection

Disease detection and monitoring play a critical role in the ongoing COVID-19 pandemic. A comprehensive detection platform that enables early virus detection can effectively stem the spread of severe acute respiratory syndrome coronavirus 2 (SARS-CoV-2). In this study, a polycrystalline silicon nanowire field-effect transistor (NWFET) was developed to detect the spike protein of SARS-CoV-2. The NWFET were fabricated through the application of sidewall spacer etching to maintain a nanowire diameter of less than 100 nm. The on–off current ratio of the transistor reached 106, and its subthreshold swing was 125 mV/decade, indicating the transistor’s strong attributes and stability. The biosensor based on this transistor reached a sensitivity of 59 mV pH−1 when used to test solutions with a pH value ranging between 6 and 9. We employed the biosensor in the detection of the SARS-CoV-2 spike protein, and the results revealed that the characteristic curve gradually shifted toward the left as the antigen of spike protein progressively increased in concentration. The limit of detection was estimated to be 0.51 ag ml−1. The results of the real-time testing of the spike protein were also successful, verifying the performance and applicability of the biosensor as a rapid screening tool for SARS-CoV-2.

Silicon Nanowire Field-Effect Transistor as Label-Free Detection of Hepatitis B Virus Proteins with Opposite Net Charges.

The prevalence of hepatitis B virus (HBV) is a global healthcare threat, particularly chronic hepatitis B (CHB) that might lead to hepatocellular carcinoma (HCC) should not be neglected. Although many types of HBV diagnosis detection methods are available, some technical challenges, such as the high cost or lack of practical feasibility, need to be overcome. In this study, the polycrystalline silicon nanowire field-effect transistors (pSiNWFETs) were fabricated through commercial process technology and then chemically functionalized for sensing hepatitis B virus surface antigen (HBsAg) and hepatitis B virus X protein (HBx) at the femto-molar level. These two proteins have been suggested to be related to the HCC development, while the former is also the hallmark for HBV diagnosis, and the latter is an RNA-binding protein. Interestingly, these two proteins carried opposite net charges, which could serve as complementary candidates for evaluating the charge-based sensing mechanism in the pSiNWFET. The measurements on the threshold voltage shifts of pSiNWFETs showed a consistent correspondence to the polarity of the charges on the proteins studied. We believe that this report can pave the way towards developing an approachable tool for biomedical applications.

Superior subthreshold characteristics of gate-all-around p-type junctionless poly-Si nanowire transistor with ideal subthreshold slope

Junctionless p-type polycrystalline silicon (poly-Si) nanowire (NW) transistor with ideal subthreshold slope (SS) is successfully demonstrated by a gate-all-around channel structure and improved fabrication processes with highly suppressed grain boundary defects in the poly-Si. The fabricated devices, whose NW width is 9.6 nm, exhibit nearly ideal SS of 60 mV dec−1 at room temperature. Furthermore, relatively high field effect mobility, small device-to-device SS variations and negligible temperature dependence are observed, indicating the device is promising for future three-dimensional integration.

Width dependence of drain current and carrier mobility in gate-all-around multi-channel polycrystalline silicon nanowire transistors with 10 nm width scale

The width dependences of characteristics of gate-all-around (GAA) polycrystalline silicon (poly-Si) transistors with 10 nm scale width were systematically investigated. The fabricated 14 nm wide GAA multi-channel poly-Si transistors exhibited excellent electrical properties including small subthreshold swing (105 mV/decade) and high Ion/Ioff ratio (∼108). Drain current normalized to effective width increases with decreasing nanowire width. It is found by the advanced split capacitance–voltage technique that both inversion carrier density and mobility are enhanced in the narrower nanowires and that the corner effect plays an important role in the drain current enhancement.

Synergetic improvements of sensitivity and specificity of nanowire field effect transistor gene chip by designing neutralized DNA as probe

Neutral DNA analogs as probes for the detection of target oligomers on the biosensors based on the field-effect transistor (FET) configuration feature advantages in the enhancement of sensitivity and signal-to-noise ratio. Herein, we used phosphate-methylated nucleotides to synthesize two partially neutralized chimeric DNA products and a fully neutralized DNA sequence and adopted a regular DNA oligomer as probes on the polycrystalline silicon nanowire (NW) FET devices. The sequences of two neutralized chimeric DNAs close to the 5′ end were alternately modified with the phosphate-methylated nucleotides, and all probes were immobilized via their 5′ end on the NW surface. The non-specific-to-specific binding ratio indicated that the two 5′-end partially neutralized chimeric DNAs featured better performance than the regular and fully neutralized DNA oligomers. The partially neutralized probe design reduces the ionic strength needed for hybridization and increases the Debye length of detection, thus promoting the detection sensitivity of FET and achieving the limit of detection of 0.1 fM. By using an appropriate probe design, applying DNA oligomers with embedded phosphate-methylated nucleotides in the FET biosensors is a promising way for gene detection with high sensitivity and specificity.

(Invited) Dual-Gate and Gate-All-Around Polycrystalline Silicon Nanowires Field Effect Transistors: Simulation and Characterization

Polycrystalline silicon nanowires (poly-SiNWs) are synthesized using sidewall spacer top-down method and classical photolithography techniques. This low-temperature (≤ 600°C) fabrication process is a low cost and fully compatible with planar complementary metal oxide semiconductor (CMOS) silicon technology. Independent biasing of each gate allows a possible threshold voltage control of the bottom gate transistors (BGT) and top gate transistors (TGT). Moreover, a new gate architecture passing from 2D to 3D, surrounding-gate transistors, called Gate-All-Around (GAA) where the gate circles the nanowire channel, allows a better electrostatic gate control. Numerical modeling of dual-gate structure and simulations are performed to estimate electrons and holes concentrations in the nanowire used as active layer versus applied gate voltages. Electrical performances of top and bottom-gate transistors are analyzed highlighting oxide-semiconducting nanowire interfaces difference in top and bottom gate configurations. Finally, GAA transistors characterization show that top channel conduction dominates when bias is applied on the surrounding gate.

(Invited) Dual-Gate and Gate-All-Around Polycrystalline Silicon Nanowires Field Effect Transistors: Simulation and Characterization

The need of miniaturization following Moore’s law has intensified research efforts on silicon nanostructures such as nanowires or nanoribbons that can be used as active part of electronic nano-devices. In this way, nanowires offer great potential as field effect transistors channel region for ultra large scale integration electronics, and also as sensitive units for the detection of charged biochemical species for sensors on CMOS platforms. Top-down approach favors patterning architectures in a planar layout, most of the SiNWs are patterned on high cost silicon-on-insulator substrates (SOI). Polycrystalline silicon SiNWs (poly-SiNWs) synthesis using sidewall spacer top down method seems to be a lower cost alternative, fully compatible with planar complementary metal oxide semiconductor (CMOS) silicon technology. In such new gate architecture passing from 2D to 3D, surrounding-gate transistors, called Gate-All-Around (GAA) where the gate circles the nanowire channel, allow a better electrostatic gate control. In our study, nanowires are elaborated using a classical fabrication method commonly used in microelectronic industry: the sidewall spacer formation technique. Assets of this technological process rest on the use of low cost lithographic tools, and the possibility to get by direct patterning numerous parallel nanowires with precise location on the substrate. We develop a low temperature (≤ 600°C) fabrication process of top-gate, bottom-gate and GAA FETs. Independent biasing of each gate allows a possible threshold voltage control of these bottom gate (BGT), top gate transistors (TGT) and GAA architecture. Electrical performances are analyzed as a function of the density of state highlighting oxide/semiconducting nanowire interfaces difference in top and bottom gate configurations. Applications for chemical and biochemical species sensing have also been investigated.

Failure of Copper Oxide Line Under High Current Density

Cu2O shows p-type semiconductor characteristics, have been investigated intensively for applications to opto-electronic devices and thin-film transistors (TFTs). Cu2O film is built by sputtering or pulsed laser deposition technique. Thermal oxidation of Cu can also create Cu2O layer, the resistivity (depending on the degree of oxidation) of the layer is controlled by temperature of heat treatment. Recently, studies on high integration such as fabrication of Cu2O nanowires were performed, but high current density due to scaling down of electronic devices induces electromigration (EM) damages. EM is a phenomenon that atom’s transport in the line by electron wind. In general, EM is one of key reasons for the failure of metal lines in electronic devices. Recently, EM failure of p-type semiconductor made of poly-crystalline silicon nanowires was studied. In this study, we conducted acceleration tests of micro-sized line of copper oxide which had p-type semiconductor characteristics to reveal electric characteristics under high current density. Straight-shaped copper oxide line samples were created on silicon substrates. Briefly, oxidation (SiO2) layer was grown on silicon substrate by thermal treatment (1173K, overnight). Cu layer with ca. 650 nm thickness was deposited on the SiO2 layer by sputtering. Cu line was fabricated through photolithography and wet-etching process. Width and length of straight test section of the line were ca. 20 um and 460 um, respectively. The Cu line was oxidized by thermal treatment (473K, 5 min). The resistivity of the copper oxide film prepared under the same conditions was 10-5 order [Ωm]. In energy dispersive X-ray spectroscopy (EDX), the O/Cu ratio of the thermal treated Cu layer was higher than that of before thermal treated. Also, the resistance of obtained copper oxide line decreased according to increasing of ambient temperature (303 to 373 K). It was considerable that the obtained copper oxide line was semiconductor materials with main component of Cu2O. Acceleration electric failure test was performed to the obtained electric lines. The sample was heated to 373K by using ceramic plate heater. Constant current (1.0 MA/cm2) applied to the obtained line by using constant current power supply and galvanometer. As shown in Fig (a), sample 1 with relatively high electric resistance was broken near the center of the test section at relatively short time (several tens minute). It seems that Joule heating was the key factor of failure, and the sample line broke at the center part with high temperature. By contrast, sample 2 with relatively low electric resistance broke near the anode side in test section at relative long time (several hundreds minute), as shown in Fig (b). In the laser microscope observations, the cross-sectional area of sample 2 was increased at the cathode side and decreased at the anode side. There is a possibility that the atomic transport due to EM was affected the failure at sample 2. In general, EM failure of metal line was observed at cathode side, since atomic transport occurred from cathode to anode with electron transport. It was reported that the semiconductor line made of poly-crystalline silicon nanowires was broken at the anode side. The failure at anode side was guessed that regrowth of grain was occurred due to Joule heating, they called this phenomenon thermally-assisted electromigration. It was suggested that similar EM failure occurred in sample 2. Acceleration electric failure tests of dumbbell-shaped copper oxide lines were performed, and failure at the anode side was observed. There is a possibility that the failure is related to thermally-assisted electromigration. It is expected that more detailed mechanism of this phenomenon can be demonstrated by the failure tests using various oxidized samples. Figure 1

Extremely Low Thermal Conductivity of Polycrystalline Silicene

By performing Green–Kubo equilibrium molecular dynamics simulations, we study thermal transport in polycrystalline silicene with grain size up to an experimental scale of 50 nm and compare it with amorphous silicene. The thermal conductivity (TC) of polycrystalline silicene with small grain size is not only lower than that of one-dimensional (1D) polycrystalline silicon nanowires with the same grain size, but also lower than that of amorphous silicene. By introducing point defects, the TC of polycrystalline silicene with rather large grain size (30 nm) is comparable to polycrystalline silicon nanowires with extremely small grain size (2 nm). Through phonon spectral energy density analysis, we reveal that the ultralow TC of polycrystalline silicene originates from the violent phonon scattering exerted by the thin boundary of grains. For higher buckling distance, the phonon properties of amorphous silicene are prominently different from those of polycrystalline silicene and are closer to those of 3D bulk or...

Individual analysis of inter and intragrain defects in electrically characterized polycrystalline silicon nanowire TFTs by multicomponent dark-field imaging based on nanobeam electron diffraction two-dimensional mapping

We visualize the grain structures for individual nanosized thin film transistors (TFTs), which are electrically characterized, with an improved data processing technique for the dark-field image reconstruction of nanobeam electron diffraction maps. Our individual crystal analysis gives the one-to-one correspondence of TFTs with different grain boundary structures, such as random and coherent boundaries, to the characteristic degradations of ON-current and threshold voltage. Furthermore, the local crystalline uniformity inside a single grain is detected as the difference in diffraction intensity distribution.

Gas Sensing Ability on Polycrystalline-Silicon Nanowire

Trace of protic gases can alter the conductivity of the polycrystalline silicon nanowire (poly-Si NW) field effect transistor (FET). The aprotic gases have no effect on the electrical parameters. The proposed mechanism is due to the surface grain boundary of poly-Si NW. The direct evidence is obtained from the comparison between single- and poly-Si NW. The electrical parameters are varied according to the relative humidity levels. Nevertheless, the water molecules can be removed by vacuum indicating that it is physical absorption on the surface. As a result, the poly-Si NW FET has potential to be a reusable device for protic gas sensor.

Temperature- and doping-concentration-dependent characteristics of junctionless gate-all-around polycrystalline-silicon thin-film transistors

The temperature effects of both gate-all-around polycrystalline silicon nanowire (GAA poly-Si NW) junctionless (JL) and inversion mode (IM) transistor devices at various temperatures (77–410 K) were investigated. The electrical characteristics of these devices, such as subthreshold swing (SS), threshold voltage (Vth), and drain-induced barrier lowering (DIBL), were also characterized and compared in this study. Moreover, JL devices with different doping concentrations at various temperatures were also discussed. Both Vth and Ion showed significant doping concentration dependences for JL devices with doping concentrations of 1 × 1019 and 5 × 1019 cm−3. However, the electrical characteristics of JL devices showed less thermal sensitivity when the doping concentration reached 1020 cm−3.

Operation characteristics of Poly-Si nanowire charge-trapping flash memory devices with SiGe and Ge buried channels

Operation characteristics of polycrystalline silicon (poly-Si) nanowire (NW) charge-trapping (CT) flash memory devices with a SiGe and a Ge buried channel are studied and compared in this work. The poly-Si NW devices with a Ge buried channel show faster programming and erasing speeds as compared to those with a SiGe one due to a lower energy barrier in tunneling layer with more Ge composition. The retention and endurance characteristics of devices with a Ge buried channel are similar to those with a SiGe one. Ge buried channel is promising to CT flash device for 3D nonvolatile memory applications.

Reduced bulk and surface states densities in metal‐induced crystallized polycrystalline silicon nanowires

Polycrystalline silicon nanowires are fabricated following sidewall spacer approach using conventional UV lithography technique. Unfortunately, solid phase crystallization of nanowires implies low electrical properties due to the poor nanowires crystal quality. As polycrystalline silicon nanowires based field effect transistors find a lot of applications, improving nanowires crystalline quality is a technological challenge. One solution studied here is metal induced lateral crystallization method, using nickel as catalyst to create oriented crystals. The comparison is done between these two crystallization techniques. Indeed, we deeply investigate silicon nanowires/insulator interface and nanowires qualities by the determination of the energy distributions of the densities of states and the surface states using the Suzuki's incremental method. This calculation confirms that metal induced lateral crystallization significantly reduces bulk and surface states densities, compared to solid phase crystallized nanowires.

Smart integration of silicon nanowire arrays in all-silicon thermoelectric micro-nanogenerators

Micro and nanotechnologies are called to play a key role in the fabrication of small and low cost sensors with excellent performance enabling new continuous monitoring scenarios and distributed intelligence paradigms (Internet of Things, Trillion Sensors). Harvesting devices providing energy autonomy to those large numbers of microsensors will be essential. In those scenarios where waste heat sources are present, thermoelectricity will be the obvious choice. However, miniaturization of state of the art thermoelectric modules is not easy with the current technologies used for their fabrication. Micro and nanotechnologies offer an interesting alternative considering that silicon in nanowire form is a material with a promising thermoelectric figure of merit. This paper presents two approaches for the integration of large numbers of silicon nanowires in a cost-effective and practical way using only micromachining and thin-film processes compatible with silicon technologies. Both approaches lead to automated physical and electrical integration of medium-high density stacked arrays of crystalline or polycrystalline silicon nanowires with arbitrary length (tens to hundreds microns) and diameters below 100 nm.

High thermosensitivity of silicon nanowires induced by amorphization

In this work, we demonstrate highly thermosensitive silicon nanowires (SiNWs) for thermal-sensing applications. Crystalline Si was amorphized by Focused Ion Beam in the fabrication process of the SiNWs, and subsequently recrystallized by a thermal annealing process to improve their electrical conductivity. A temperature coefficient of resistance (TCR) from −8000ppm/K to −12,000ppm/K was measured for the SiNWs. This large negative TCR is attributed to the boundary potential barrier of 110meV between silicon crystallites in the poly crystalline SiNWs.

Preparation of Silicon Nanowire Field-effect Transistor for Chemical and Biosensing Applications.

Surveillance using biomarkers is critical for the early detection, rapid intervention, and reduction in the incidence of diseases. In this study, we describe the preparation of polycrystalline silicon nanowire field-effect transistors (pSNWFETs) that serve as biosensing devices for biomarker detection. A protocol for chemical and biomolecular sensing by using pSNWFETs is presented. The pSNWFET device was demonstrated to be a promising transducer for real-time, label-free, and ultra-high-sensitivity biosensing applications. The source/drain channel conductivity of a pSNWFET is sensitive to changes in the environment around its silicon nanowire (SNW) surface. Thus, by immobilizing probes on the SNW surface, the pSNWFET can be used to detect various biotargets ranging from small molecules (dopamine) to macromolecules (DNA and proteins). Immobilizing a bioprobe on the SNW surface, which is a multistep procedure, is vital for determining the specificity of the biosensor. It is essential that every step of the immobilization procedure is correctly performed. We verified surface modifications by directly observing the shift in the electric properties of the pSNWFET following each modification step. Additionally, X-ray photoelectron spectroscopy was used to examine the surface composition following each modification. Finally, we demonstrated DNA sensing on the pSNWFET. This protocol provides step-by-step procedures for verifying bioprobe immobilization and subsequent DNA biosensing application.

Preparation of Silicon Nanowire Field-effect Transistor for Chemical and Biosensing Applications

Surveillance using biomarkers is critical for the early detection, rapid intervention, and reduction in the incidence of diseases. In this study, we describe the preparation of polycrystalline silicon nanowire field-effect transistors (pSNWFETs) that serve as biosensing devices for biomarker detection. A protocol for chemical and biomolecular sensing by using pSNWFETs is presented. The pSNWFET device was demonstrated to be a promising transducer for real-time, label-free, and ultra-high-sensitivity biosensing applications. The source/drain channel conductivity of a pSNWFET is sensitive to changes in the environment around its silicon nanowire (SNW) surface. Thus, by immobilizing probes on the SNW surface, the pSNWFET can be used to detect various biotargets ranging from small molecules (dopamine) to macromolecules (DNA and proteins). Immobilizing a bioprobe on the SNW surface, which is a multistep procedure, is vital for determining the specificity of the biosensor. It is essential that every step of the immobilization procedure is correctly performed. We verified surface modifications by directly observing the shift in the electric properties of the pSNWFET following each modification step. Additionally, X-ray photoelectron spectroscopy was used to examine the surface composition following each modification. Finally, we demonstrated DNA sensing on the pSNWFET. This protocol provides step-by-step procedures for verifying bioprobe immobilization and subsequent DNA biosensing application.