Abstract

Micro and nanotechnologies are called to play a key role in the fabrication of small and low cost sensors with excellent performance enabling new continuous monitoring scenarios and distributed intelligence paradigms (Internet of Things, Trillion Sensors). Harvesting devices providing energy autonomy to those large numbers of microsensors will be essential. In those scenarios where waste heat sources are present, thermoelectricity will be the obvious choice. However, miniaturization of state of the art thermoelectric modules is not easy with the current technologies used for their fabrication. Micro and nanotechnologies offer an interesting alternative considering that silicon in nanowire form is a material with a promising thermoelectric figure of merit. This paper presents two approaches for the integration of large numbers of silicon nanowires in a cost-effective and practical way using only micromachining and thin-film processes compatible with silicon technologies. Both approaches lead to automated physical and electrical integration of medium-high density stacked arrays of crystalline or polycrystalline silicon nanowires with arbitrary length (tens to hundreds microns) and diameters below 100 nm.

Highlights

  • In those application scenarios where residual heat is present thermoelectricity may be exploited as a source of energy autonomy

  • Miniaturization and large volume fabrication are significant characteristics of silicon technologies and, many sensors and auxiliary electronic and communication devices are fabricated with such technologies

  • Single crystalline and polycrystalline silicon nanowires of arbitrary length and with effective diameters below 100 nm have been successfully obtained so that phonon scattering phenomena will lead to high enough ZT values

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Summary

Introduction

A planar micro thermo-electric generator (TEG) can be obtained by fabricating a suspended silicon platform and defining a low density flat Si NWs array in a silicon-on-insulator (SOI) wafer with a nano-thick device layer [2]. A second approach is using state of the art submicron CMOS technologies to obtain more robust structures and higher density arrays of Si NWs. In this case the microgenerator is of vertical architecture, which adapts better to naturally occurring thermal gradients, but the ‘height’ of the vertically defined nanowires is limited to the order of one micron, which is not large enough to develop significant temperature differences across them [4].

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