Polycide Gate Research Articles

0.35 μm Technologies in Japan

AbstractThis paper describes silicide and salicide technologies in Japan for 0.35 μm CMOS ULSIs and beyond. Polycide gate electrodes have been developed for CMOS devices from 1.0 μm to 0.35 μm design rule regime, in which Wsi2 has been used dominantly as a silicide gate material. On the other hand, silicide films are formed selectively on source/drain diffusion layers by salicide techniques, in which TiSi2 is used as a salicide material. TiSi2 is also used as a salicide material of both gate electrodes and source/drain diffusion layers for dual gate (n+/p+) CMOS. The TiSi2 thin film is formed by Ti sputtering and subsequent rapid thermal annealing. A preamorphization technique before Ti sputtering has been developed to obtain equal silicide properties on p+ and n+ diffusion layers. A high-temperature Ti sputtering technique has been developed in conjunction with pre-amorphization. CoSi2 and NiSi have also been developed as salicide materials for quartermicron CMOS and beyond.

A Simple and Efficient Pretreatment Technology for Selective Tungsten Deposition in Low-Pressure Chemical Vapor Deposition Reactor

In this paper we develop a two-step pretreatment method which is a simple but effective cleaning process that can be used to achieve a high deposition rate and excellent interface characteristics, as well as improve the selectivity. In the first step, we use CF4/O2 mixing gases as a plasma etching system without substrate bias. The removal of damage and contaminants by reactive ion etching (RIE) during contact hole opening can thus be obtained. We consider that the role of oxygen is first to oxidize the polymer residues (i.e., fluorocarbons like Cx Fy ) and the RIE-damaged regions on the silicon surface, and it is then followed with CF4 to remove these oxides. In experiments, the plasma modification rate can be controlled at 120 Å/min. Results of the high deposition rate, smooth interface, low selectivity loss and the other improvements are observed. These are superior to those of cases without pretreatment. The second step is that anhydrous HF cleaning was used to remove surface oxide which was formed during the first step. Obviously, this new cleaning technology is very efficient not only for contact hole pretreatment but also for polysilicon materials. This also implies that this technology may have potential for polycide gate applications.

Gate oxide damage reduction using a protective dielectric layer

Gate oxide damage from charge entering through the top surface of the gate electrode during plasma ashing, ion implantation, and LDD spacer oxide etching was measured using antenna structures. Significant charge damage to the 9.0 nm-thick gate oxide was detected for each of these processes. The damage was reduced by using a protective dielectric layer, in this case a thermally deposited TEOS oxide over the polycide gate electrode before gate definition. The dielectric appears to block charge penetration into the antenna. Damage can be reduced further by increasing the thickness of the dielectric layer; for a sufficiently thick layer (about 150 nm), charge entering through the top surface of the antenna was effectively eliminated.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A 0.6 micron triple level metal process for high performance application specific integrated circuits

This paper describes a 0.6 micron triple level interconnect scheme for ASIC application. This interconnect scheme has been used with 0.6 micron twin well CMOS technology having polycide gates. Excellent planarization of BPSG films was achieved at a low reflow temperature by using TEOS/0 3-based APCVD BPSG. Sandwich layers of TiW/Al-1%Cu/TiW were used for interconnects. A void-free Inter-Metal-Oxide (IMO) planarization with good device reliability was achieved using a combination of silicon-rich silane-based PECVD oxide, TEOS-based PECVD oxide and SOG etchback process. In order to achieve the maximum packing density, metal 3 is used as a routing layer and has the same pitch as metal 1 and metal 2 layers. It has been demonstrated that the device and the interconnect reliabilities for this metallization scheme are excellent.

Electrical effects due to dopant redistribution in titanium and cobalt polycide gate MOS capacitor structures

The effects of titanium and cobalt silicidation of the polysilicon gate in MOS capacitors on the electrical properties of the gate oxide are investigated. For the titanium polycide gate the value of the flat-band voltage is about 20 to 30 mV higher than for the polysilicon gate. A similar difference is observed in the value of the barrier height at the polycide/oxide interface from the Fowler-Nordheim characteristics. This phenomenon is explaind by postulating that phosphorus outdiffusion occurs from the polysilicon during the titanium silicidation process. For the cobalt polycide gate, no such differences with respect to the polysilicon gate are observed.

Decrease of gate oxide dielectric constant in tungsten polycide gate processes

The gate oxide thickness for tungsten (W) polycide gate processes is studied, with tungsten silicide (WSi/sub x/) deposited either by chemical vapor deposition (CVD) or sputtering. For WSi/sub x/ deposited by CVD, it is found that the effective thickness of gate oxide as determined by CV measurement increases in all cases if the annealing temperature is 900 degrees C or higher. However, high-resolution transmission electron microscopy (TEM) measurement indicates that the physical thickness does not change after a 900 degrees C anneal. In this case, the dielectric constant of the gate oxide decreases by 7%. As the annealing temperature increases to 1000 degrees C, CV and TEM measurements give the same thickness and the decrease of the dielectric constant disappears. In contrast, for WSi/sub x/ film deposited by sputtering, annealing at 900 degrees C has no effect on the gate oxide thickness as measured by CV and TEM.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

New hot-carrier degradation mode in PMOSFETs with W gate electrodes

Hot-carrier degradation of W gate PMOSFETs, which are surface-channel devices because of the work function of W, has been investigated in comparison with polycide (WSi/sub x//n/sup +/ poly-Si) ones. In W gate PMOSFETs, transconductance g/sub m/ and threshold voltage V/sub th/ decrease on the drain avalanche hot-carrier (DAHC) stress, and Delta g/sub m//g/sub m0/ and Delta V/sub th/ become minimum at V/sub G/ equivalent to V/sub D//2. By using the charge-pumping technique, it is found that, after stressing at the same stress condition, the interface state density of W gate devices is about 10 times larger than that of polycide ones but the densities of trapped electrons are almost equal. These results indicate that the difference of hot-carrier degradation between W and polycide gate devices is mainly caused by the difference of the interface state density. >

SNMS studies of ULSI gate interconnection structures

Polycide gate structures are widely used in ULSI (Ultra Large Scale Integration) devices. The distribution of the dopant between the various layers is of major concern. The effects of the fluorine incorporated during WSi2 deposition have been discussed because fluorine may diffuse into the gate oxide. We have studied the redistribution of boron, phosphorus and fluorine in WSi2/poly/SiO2/poly/SiO2/Si (bulk) gate structures by using hot e-gas SNMS and nuclear analyses (RBS/NRA), in samples subjected to thermal treatments that simulate the different steps of the ULSI fabrication sequence.

The Effect of Amorphous Silicon Layer in PE-CVD Titanium Polycide Gate Dielectrics

AbstractTitanium silicide (TiSix), used as polycide gate consists of TiSi1.1 and amorphous silicon (a—Si), was deposited by Plasma Enhanced Chemical Vapor Deposition method (PE—CVD). The effect of a—Si layer in PE—CVD Ti polycide gate dielectrics has been studied. In order to evaluate the a—Si layer effect, three types of samples were prepared on gate SiO2 film with following structures: a) a—Si / TiSil.1 / a—Si / phosphorus (P) doped poly—Si, b) a—Si / TiSi1.1 / non—doped poly—Si / P doped poly—Si and c) a—Si / TiSi1.1 / P doped poly—Si, respectively. Furthermore, in order to avoid the influence of native oxide existence at the interface, the pre—cleaning treatment was performed in—situ on the poly—Si film surface before TiSi1.1 film deposition. The gate dielectric strengths of these samples indicate that the gate dielectric degradation in PE—CVD Ti polycide gate is greatly dependent on Si under layer crystallization. It is effective using a—Si film as the under layer in decreasing the gate dielectric degradation. This is due to the Ti oxide interlayer, formed at the interface of TiSi2.0 and poly—Si films, whichrestrains the TiSix local penetration.

Effects of Arsenic Segregation and Electron Trapping on the Capacitance-Voltage Behavior of Polysilicon and Polycide Gates

AbstractThis paper discusses the effects of dopant segregation and electron trapping on the capacitance-voltage characteristics of arsenic-implanted polysilicon and amorphous Si gate MOS structures fabricated with and without a TiSi2 layer. The effects of gate bias, annealing temperature, silicide formation and polysilicon grain microstructure on the C-V characteristics have also been studied. The results show that insufficient arsenic redistribution at 800°C, coupled with carrier trapping at polysilicon grain boundaries and dopant segregation in TiSi2 causes depletion effects in the polysilicon gate and in turn, an anomalous capacitance-voltage behavior. The depletion tends to increase the “effective” gate oxide thickness and thereby degrade MOS device performance. Higher temperature anneals (≥ 900°C) are sufficient to achieve degenerate doping in the polysilicon gates and avoid the depletion effects.

The Effect of Amorphous Silicon Layer in Pe-Cvd Titanium Polycide Gate Dielectrics

ABSTRACTTitanium silicide (TiSix), used as polycide gate consists of TiSi1.1 and amorphous silicon (a-Si), was deposited by Plasma Enhanced Chemical Vapor Deposition method (PE-CVD). The effect of a-Si layer in PE-CVD Ti polycide gate dielectrics has been studied. In order to evaluate the a-Si layer effect, three types of samples were prepared on gate SiO2 film with following structures : a) a-Si / TiSi-1.1 / a-Si / phosphorus (P) doped poly-Si, b) a-Si / TiSi-1.1 / non-doped poly-Si / P doped poly-Si and c) a-Si / TiSi1.1 / P doped poly-Si, respectively. Furthermore, in order to avoid the influence of native oxide existence at the interface, the pre-cleaning treatment was performed in-situ on the poly-Si film surface before TiSi1.1 film deposition. The gate dielectric strengths of these samples indicate that the gate dielectric degradation in PE-CVD Ti polycide gate is greatly dependent on Si under layer crystallization. It is effective using a-Si film as the under layer in decreasing the gate dielectric degradation . This is due to the Ti oxide interlayer, formed at the interface of TiSi2.0 and poly-Si films, which restrains the TiSix local penetration.

A Refined Polycide Gate Process with Silicided Diffusions for Submicron MOS Applications

A polycide process with silicided diffusions is presented. This allows simultaneous use of mutually different silicides on the gate electrode and on the respective source and drain areas. The novel technique was used to fabricate MOSFETs and gate electrodes and self‐aligned on source/drain regions. Respective sheet resistivities were 5 and 7–8 Ω/□ and no degradation effects were observed. A comparison with the more conventional salicide concept is made and several advantages are elucidated.

25-ns 256K×1/64K×4 CMOS SRAM's

Through a metal option, a 256K word/spl times/1-bit and a 64K word/spl times/4-bit CMOS SRAM organization has been obtained. A fast access time has been achieved with a short bit-line structure and a data-bus precharging technique which minimize the bit-line and data-bus delay. A feedback-controlled address-transition-detector circuit has been adopted to assure the fast access time in the presence of address skew. A 1.0-/spl mu/m double-polysilicon and single-metal process technology with a polycide gate offers a memory cell size of 90 /spl mu/m/SUP Z/ and a chip size of 47.4 mm/SUP 2/.

Possible applications of tantalum silicide for very-large-scale integration technology

The possibility of depositing TaSi 2 by sputtering and chemical vapour deposition (selective and non-selective deposition) opens a wide variety of applications for this material in very-large-scale integration technology. The following examples are briefly discussed: (1) polycide gate metallization; (2) silicide gate metallization; (3) diffusion barrier properties; (4) source-drain silicidation; (5) planarization by contact hole filling.

A fast 8Kx8 CMOS SRAM with internal power down design techniques

A 35-ns 8K/spl times/8 CMOS SRAM with address-transition detection design techniques and a novel architecture is described. This design uses a 1.5-/spl mu/m HCMOS twin-well process with polycide gates. A technique for generating internal timing which is impervious to address skew and glitches has been developed. At long cycle times the circuit automatically powers down to a 8-mA active current level with the part selected.

Development of the self-aligned titanium silicide process for VLSI applications

A manufacturable self-aligned titanium silicide process which simultaneously silicides both polysilicon gates and junctions has been developed for VLSI applications. The process produces silicided gates and junctions with sheet resistances of 1.0-2.0 Ω/square. This paper describes the application of the self-aligned titanium silicide process to NMOS VLSI circuits of the 64K SRAM class with 1-µm gate lengths. Comparison of circuit yield data and test structure parameters from devices fabricated with and without the silicidation process has demonstrated that the self-aligned silicide process is compatible with both VLSI NMOS and CMOS technologies. The self-aligned titanium silicide process has some very significant manufacturing advantages over the more conventional deposited silicide on polysilicon technologies. In particular, the problems associated with etching and depositing a polycide gate stack are eliminated with the self-aligned process since the polycide etch is replaced with a much more straightforward polysilicon only etch. As gate lengths, gate oxide thicknesses, and source-drain junction depths are scaled, linewidth control, etch selectivity to the underlying gate oxide, and cross-sectional profile control become more critical. The stringent etch requirements are more easily satisfied with the self-aligned silicide process.

Development of the Self-Aligned Titanium Silicide Process for VLSI Applications

A manufacturable self-aligned titanium silicide process which simultaneously silicides both polysilicon gates and junctions has been developed for VLSI applications. The process produces silicided gates and junctions with sheet resistances of 1.0-2.0 Omega/square. This paper describes the application of the self-aligned titanium silicide process to NMOS VLSI circuits of the 64K SRAM class with 1-/spl mu/m gate lengths. Comparison of circuit yield data and test structure parameters from devices fabricated with and without the silicidation process has demonstrated that the self-aligned silicide process is compatible with both VLSI NMOS and CMOS technologies. The self-aligned titanium silicide process has some very significant manufacturing advantages over the more conventional deposited silicide on polysilicon technologies. In particular, the problems associated with etching and depositing a polycide gate stack are eliminated with the self-aligned process since the polycide etch is replaced with a much more straightforward polysilicon only etch. As gate lengths, gate oxide thicknesses, and source-drain junction depths are scaled, Iinewidth control, etch selectivity to the underlying gate oxide, and cross-sectional profile control become more critical. The stringent etch requirements are more easily satisfied with the self-aligned silicide process.

Rapid Thermal Annealing of Tisi2 for Interconnects

ABSTRACTA self-aligned polycide gate interconnect process has been developed at STL in order to reduce the RC delays in existing and planned MOS circuits. This process has been chosen due to its ease of implementation into an existing process line. Incoherent lamp annealing is used to form the silicide after the deposition of titanium over patterned polysilicon.This paper will discuss the various materials and processes considered, outlining the significant attributes of each. The factors which must be controlled to achieve a practical process are discussed, together with the degree of redistribution of dopants and the role of other impurities.

Properties of low-pressure CVD tungsten silicide for MOS VLSI interconnections

Low-pressure chemical vapor deposition of tungsten silicide has been done and the properties of the deposited films have been studied to determine the process compatibility and suitability to form gate electrodes and interconnections in MOS VLSI applications. The silicide was deposited on single-crystal silicon and on oxidized silicon with and without a coating of polycrystalline silicon film. Auger analysis of the As-deposited films showed absence of any contaminants in it. X-ray diffraction and transmission electron microscopy showed that As-deposited films were microcrystalline with grains smaller than 30 Å and upon annealing became polycrystalline WSi <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> with hexagonal structure at 500°C and tetragonal structure at or above 600°C with a corresponding decrease in resistivity from 600-900 µΩ . cm to 35-60 µΩ . cm depending upon anneal temperature and time. No appreciable change in the thickness of the silicide was found during the high-temperature anneals. Silicon-rich silicide films remained stable, smooth, and free of cracks through high-temperature anneals and oxidations, and their adherence to the wafer remained excellent. On the other hand, metal-rich films had overall inferior properties. Thermal oxidation of WSi <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> on polysilicon in dry oxygen in the temperature range of 900 to 1100°C was found to be similar to that of silicon except the linear regime of oxidation was extremely rapid and the entire process could be modeled by a parabolic equation <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">X^{2) = Bt</tex> with an activation energy of 1.7 eV. MOS capacitors were fabricated with silicide and polycide gate electrodes. Polysilicon thickness variation from 0 to 5000 Å had no adverse effect on the electrical characteristics or mechanical integrity of the devices. In all cases, low values of N <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</inf> (1 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">10</sup> -7 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">10</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> ) and N <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">it</inf> (< 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">10</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> . eV <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> ) and high gate oxide dielectric strength ( <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">\sime 8</tex> MV/cm) were obtained.

Work function measurement of tungsten polycide gate structures

Three MOS gate structures; polysilicon, tungsten silicide and tungsten polycide, were fabricated and their workfunctions measured with the high frequency C-V technique. The work functions were 4.14 ev and 4.82 ev for phosphorus doped polysilicon and silicon-rich tungsten silicide, respectively. The tungsten polycide structure, however, showed a variance between 4.14 ev and 4.38 ev for different experiments. The polycide MOS device threshold was about 0.15 volt higher than that of polysilicon. Phosphorus out-diffusion and tungsten diffusion along polysilicon grain boundaries were postulated to explain this phenomenon.