Gate oxide damage reduction using a protective dielectric layer

Abstract

Gate oxide damage from charge entering through the top surface of the gate electrode during plasma ashing, ion implantation, and LDD spacer oxide etching was measured using antenna structures. Significant charge damage to the 9.0 nm-thick gate oxide was detected for each of these processes. The damage was reduced by using a protective dielectric layer, in this case a thermally deposited TEOS oxide over the polycide gate electrode before gate definition. The dielectric appears to block charge penetration into the antenna. Damage can be reduced further by increasing the thickness of the dielectric layer; for a sufficiently thick layer (about 150 nm), charge entering through the top surface of the antenna was effectively eliminated.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>