Damage to thin gate oxide during lightly doped drain spacer oxide etching

Abstract

Charge buildup damage to gate oxide during lightly doped drain (LDD) spacer oxide etch was studied by measuring gate leakage of fully processed transistors over thin oxide attached to area-intensive or edge-intensive polycide antenna structures over thick oxide. Wafers were etched at the LDD spacer oxide etch step for various overetch times ranging from −7% to +35%. It was found that gate oxide damage from charge buildup depended strongly on spacer overetch time. No charge buildup was detected before endpoint (defined as the time required to completely remove oxide from flat silicon surfaces—the polycide has a cap oxide layer on it, so the gate electrode is not exposed at endpoint), but significant charge buildup occurred through the polycide surface when etching was continued past endpoint. Gate leakage failures for transistors attached to large area-intensive antennas increased monotonically with overetch time, leading to 100% failure after 20%–30% overetch. This charge buildup damage began to occur even before the cap oxide was completely removed and the gate electrode was exposed to the plasma, suggesting that either the tetraethylorthosilicate oxide itself was not perfectly insulating or it became leaky after exposure to this high-energy oxide etch plasma with a dc bias of about −600 V.