Effect of plasma overetch of polysilicon on gate oxide damage

Abstract

Modeling and previous experiments have indicated that charging damage during metal–oxide semiconductor (MOS) polysilicon gate etching occurs just before endpoint when the last of the exposed polysilicon can collect excess plasma currents that cause damage by flowing through the gate oxide. During overetch, this damage mechanism is suppressed by the poor collection efficiency of the exposed polysilicon edges, so damage from this mechanism is expected to remain constant during this period. Although there is an additional edge damage mode where damage can increase during overetch, we here report results showing a decrease in damage with overetch time. The experiment consisted of two lots of fully processed complementary MOS wafers where the polysilicon overetch percentage was varied from 0% to 110%. The etch tool was a triode system that showed antenna dependent charging damage. The test structures were large area capacitors with a 10.5 nm thin oxide whose breakdown statistics were measured after the full process, including anneals. Both the n-channel and p-channel devices showed damage which decreased with overetch time. The damage was significantly worse for the n-channel devices—the mean n-channel gate oxide breakdown voltage was 3 V at endpoint compared to 11.5 V after 110% overetch. The effect was repeated in that both lots showed the same results. The results indicate an apparent annealing during overetch. In the past, radio frequency (rf) annealing has been reported for e-beam damage with a proposed mechanism involving rf heating and carrier motion. We consider this unlikely and suspect that low plasma currents collected by the gate edge could be playing a role in the annealing; however, etching of the exposed gate oxide during overetch may also be important. The n- and p-channel differences can be explained by a voltage drop across the n well which reduces the tunnel current through the p-channel gate oxides.