A 0.6 micron triple level metal process for high performance application specific integrated circuits

Abstract

This paper describes a 0.6 micron triple level interconnect scheme for ASIC application. This interconnect scheme has been used with 0.6 micron twin well CMOS technology having polycide gates. Excellent planarization of BPSG films was achieved at a low reflow temperature by using TEOS/0 3-based APCVD BPSG. Sandwich layers of TiW/Al-1%Cu/TiW were used for interconnects. A void-free Inter-Metal-Oxide (IMO) planarization with good device reliability was achieved using a combination of silicon-rich silane-based PECVD oxide, TEOS-based PECVD oxide and SOG etchback process. In order to achieve the maximum packing density, metal 3 is used as a routing layer and has the same pitch as metal 1 and metal 2 layers. It has been demonstrated that the device and the interconnect reliabilities for this metallization scheme are excellent.