Polycide Gate Research Articles

Investigation of Sidewall Oxidation on WSix Gates for Nano-Scale NAND Flash Memory Cells

Extrusions on W–polycide (WSix) gate sidewalls, sheet resistance (Rs), and device characteristics as well as memory cell performance for 70 nm NAND flash memory cells are investigated. To prevent the formation of unstable W–Si–O compounds, oxidation of WSix gate sidewalls prior to oxygen plasma ashing for source/drain photo resist removal is implemented, and then WSix extrusion can be absolutely suppressed. Moreover, the sheet resistance of a WSix gate can be improved near 40% by additional sidewall oxidation due to enlarged grain size and reduction in surface roughness; thus, the program voltage of memory cells can be significantly improved more than 1 V. Simultaneously, the saturation current of n-type metal–oxide–semicondutor field effect transistor (NMOSFET) shifts less than 4%, and cell threshold voltage fluctuations resulting from floating gate coupling are not obviously changed.

A Unique Dual-Poly Gate Technology for 1.2-V Mobile DRAM with Simple In situ n<tex>$^+$</tex>-Doped Polysilicon

Highly manufacturable sub-100-nm 1.2-V mobile dynamic random access memory (DRAM) having full functionality and excellent reliability have been successfully developed. A unique and simple DRAM technology with dual-gate CMOSFET was realized using plasma-nitrided thin gate oxide and p/sup +/ poly gate formed by BF/sub 2/ ion implanted compensation of in situ phosphorus (n/sup +/) doped amorphous silicon gate. Using this technology, boron penetration into the channel, gate poly depletion, and dopant interdiffusion between n/sup +/- and p/sup +/-doped WSi/sub x/-polycide gates were successfully suppressed. In addition, a negatively biased word line scheme and a storage capacitor with laminated high-/spl kappa/ Al/sub 2/O/sub 3/ and HfO/sub 2/ dielectrics were also developed to achieve mobile DRAM operating at 1.2 V with excellent performance and reliability.

Impact of Polymetal Gate Etch Post-Cleaning on Data Retention Time in Sub-micron DRAM Cells

We have investigated the impact of gate etch post-cleaning process on the tail distribution of data retention time in dynamic random access memory (DRAM) cells having polymetal (W/WNx/Poly-Si) gate device based on the fully mature technology of sub-micron DRAM. In this paper, we propose the optimized gate etch post-cleaning condition in polymetal gate device to guarantee the characteristics of DRAM data retention time comparable to that of the conventional polycide (WSix/Poly-Si) gate etch post-cleaning process. In addition, for the first time, we have verified that the effective removal of the unwanted residue generated by gate etch improves the interface quality of the remaining oxide at the gate edge, resulting in improving the tail component of data retention time.

Effect of TaSi2 and WSi2 deposition on interfacial defects and Fowler-Nordheim injection in polycide gate SiO2 MOS capacitors

In this work we have studied the effect of TaSi 2 and WSi 2 silicide deposition on the electrical properties of non-degraded dry-wet-dry oxides (-7.2 nm) in polycide/SiO 2 /Si structures. WSi 2 and TaSi 2 silicides are deposited by chemical vapor deposition and by sputtering respectively. Particular attention has been paid to the non-uniform density (D it ) energetical distribution of amphoter Si/SiO 2 interface states, to the presence of acceptor and/or donor interface states (D imp ) due to impurities induced by the polycide gate process, and to Fowler-Nordheim (FN) barrier heights at both injecting interfaces. We have observed that i) TaSi 2 structures present more important D it densities that WSi 2 ones, ii) TaSi 2 samples reveal the presence of acceptor D imp interface states probably due to SiO 2 contamination by elements of the I and II groups during the silicide deposition, iii) the polycide type has a strong impact on both FN barrier heights. Finally the influence of gate oxide nitridation in N 2 O has been considered both in TaSi 2 and WSi 2 structures: i) the nitridation reduces D it density but this reduction is more pronounced in the case of TaSi 2 devices, ii) the nitridation does not reduce D imp density in TaSi 2 structures.

Effects of the Process Variable on Sputtered TiSix Polycide Gate Electrodes for sub-0.15 μm Memory Device Application

We examine effects of the process variables of transistor gate structures on material and electrical properties of films and patterned polycide gate lines at sub-0.15 μm regime. The process variables include molar ratio of Si/Ti in composite targets 2.2, 2.3, and 2.4), sputter deposition temperature, film thickness, rapid thermal annealing (RTA) process condition, and postannealing in a furnace. At high Si precipitate formation is highly pronounced at the film surface as RTA temperature increases and contributes to the increase in surface roughness of the films. Moreover, processes of higher x targets show a greater number of add-on particles and more retarded phase transformation. The RTA process after film deposition completely transforms films to phase even at very fine lines when annealed at 800°C or higher for 20 s. The maximum thermal budget allowed for postannealing is 800°C for 60 min, where no appreciable thermal degradation is shown in bar resistance regardless of target composition. At this postannealing condition, excellent bar resistance (∼4.4 Ω/□) and thermal stability are shown at 0.12 μm linewidth when films were sputtered at 200°C. films sputtered at 500°C show a stronger (040) C54 preferred orientation and greater degraded thermal stability than the films deposited at 200°C, and exhibit a bar resistance of ∼5 Ω/□ at 0.12 μm linewidth. © 2001 The Electrochemical Society. All rights reserved.

Improvement of sheet resistance and gate oxide integrity using phosphorus ion implantation in tungsten polycide gate

An implantation of phosphorus is used in tungsten polycide gate process, and the effects of implantation on the reduction of resistance and characteristics of GOI (Gate Oxide Integrity) were investigated. The sheet resistance of gate electrode decreases with increase of phosphorus implant dose and energy as increase of grain size. The depletion effects of gate polysilicon at reverse biases were found in unimplanted tungsten polycide gate due to the out-diffusion of dopant atoms in buffer polysilicon layers during activation anneals. However, the depletion effects of gate polysilicon were effectively suppressed by the implantation of phosphorus. The lifetime of gate oxide was degraded several orders of magnitude for the high-energy implanted samples. Therefore, there is optimum energy for phosphorus implantation into gate electrode to improve the resistance of tungsten polycide gate electrode and the depletion effects of gate polysilicon.

The influence of post annealing on oxide charge-to-breakdown in tungsten polycide gate technology

The dependence of Q BD on the combined post annealing conditions of RTA and FA in the tungsten polycide gate technology has been experimentally investigated. In the case of RTA to be processed after FA, Q BD is controlled by the amount of fluorine diffused into the oxide, and then it is decreasing as increasing RTA temperature and time. However, in the vice-versa case, Q BD shows the poor characteristics because of the effect of lightly activated polysilicon. Based on these experimental results, the combined post annealing with FA/RTA sequence is useful to obtain the high Q BD performance.

Effects of Rapid Thermal Annealing on Cobalt Silicided p+ poly-Si Gates Fabricated by BF2+ Implantation into Bilayered CoSi/a-Si Films

The cobalt polycide gate formed by implanting BF2+ ions into the bilayered CoSi/a-Si films and the subsequent rapid thermal anneal has been studied. The resulting gate oxide integrity is characterized with respect to various silicide thicknesses and implantation energies. Significant degradation in gate oxide integrity and flat-band voltage shift were found with increasing silicide thickness and annealing temperature, especially for the thicker CoSi2 films, which is attributable to severe boron penetration. Although a thinner silicide can achieve excellent gate dielectric reliability, it will lead to poor high-temperature thermal stability. Moreover, shallower implantation depth and lower annealing temperature, which sustain less boron penetration, would cause the poly-Si gate depletion effects. Therefore, appropriate conditions, which comprise the CoSi2 thickness, the implantation energy, and the annealing temperature, should be employed to optimize the device performance while retaining the thin dielectric reliability.

Reliability improvement of EEPROM by using WSi2 polycide gate

Recent technology fabrication of EEPROM developed by STMicroelectronics involves tungsten-based polycide for the gate of the transistors. The EEPROM design is based on one floating gate. The main objective was to increase the data retention capability on product using this polycide, and this after cycling. Thus, we have set up a new process called integrated process involving a cluster tool which avoids any contamination during the manufacturing of the polycide stacked layers in comparison with the standard process. In addition, the tungsten chemistry induces an insertion of fluorine in the tunnel oxide. The presence of the fluorine is verified and can explain the modification of the threshold voltages and the evolution of the programming window. Analyses of test cells and product vehicles were made. This new process improves the data retention capability of the EEPROM after one million cycles, and also decreases the cumulative percentage of defects; these results were good enough to insert this process in the production line.

Elimination of gate oxide damage during electron cyclotron resonance plasma etching of the tungsten polycide gate structure (WSi/poly-Si)

Oxide damage during the over etch step of a polycide gate structure is studied. Seven process parameters of the electron cyclotron resonance (ECR) plasma etching system are systematically investigated. These parameters include: rf power, microwave power, main coil and subcoil currents, Cl2 and O2 gas flow rate, and pressure. The results show that damage depends strongly on only three parameters: rf power, subcoil current, and O2 flow rate. As a result, a highly anisotropic, damage and poly-Si residue free etch of the polycide gate structure, with a high etch rate, has been achieved. These etch characteristics are critical for manufacturing the next generation of IC products.

A comparison of hot-carrier degradation in tungsten polycide gate and poly gate p-MOSFETs

A study is made of hot-carrier immunity of tungsten polycide and of non-polycide, n/sup +/ poly gate, buried-channel p-MOSFETs, under conditions of maximum gate current injection. Increased hot-carrier degradation is observed for WSi/sub x/ p-MOSFETs under low drain voltage stress, where trap filling by injected electrons is the dominant degradation process. Stress-induced damage evaluated by gate-to-drain capacitance C/sub gd//sup s/ measurement shows increased susceptibility to electron trapping in the WSi/sub x/ device. F-induced oxide bulk defects introduced during polycidation may be responsible for the increased trapping observed. In addition, a significant decrease in electron detrapping rate is observed, which suggests a deeper energy distribution of F-related traps. The greater susceptibility to electron trapping, coupled with a decrease in electron detrapping rate, result in the reduction in DC hot-carrier lifetime over four orders of magnitude (based on /spl Delta/V/sub t/=50 mV criterion) under normal operating voltages. As hot-carrier effects in p-MOSFETs continue to be a concern for effective channel lengths less than 0.5 /spl mu/m, the reduced hot-carrier lifetime of WSi/sub x/ p-MOSFETs suggests that WF/sub 6/-based silicidation may not be appropriate for deep submicrometer CMOS devices.

Reduction of boron penetration for a p + polycide gate by using cobalt silicides as a boron diffusion source

A scheme for forming a p + polycide gate is described, by using BF 2 implantation into CoSi/poly-Si bilayer films and subsequent annealing. Instead of the conventional BF 2 implantation into thin poly-Si films, this scheme employs the CoSi layer as an implant barrier as well as a boron diffusion source to retard the boron diffusion. The improved gate oxide integrity and the reduced flat-band voltage shift can be obtained without causing other side effects. In addition, it is found that the stack layer of CoSi/a-Si can serve as an excellent implant barrier for suppressing the boron penetration through a gate oxide.

Hot-carrier reliability of non-degenerately doped tungsten polycide gate buried-channel p-MOSFETs

A polysilicon-depletion effect is observed for the non-degenerately doped polysilicon layer of a tungsten silicide-polysilicon gate stack of buried-channel p-MOSFETs, but not for n-MOSFETs with a polysilicon layer of the same doping concentration. A lower current drive and transconductance, coupled with a higher subthreshold slope, will result in poorer dynamic performance for p-MOSFETs having a lower doped polysilicon layer. The potential drop across the lower doped polysilicon layer results in lower gate currents. Consequently the p-MOSFETs with a lower doped polysilicon layer are more resistant to hot-carrier induced degradation and have higher hot-carrier lifetimes. Thus there exists an optimum polysilicon doping concentration for tungsten-polycide devices and the latter is dependent on the desired electrical performance and hot-carrier reliability of buried-channel p-MOSFETs.

Decoupled Plasma Source Technology: Process Region Choices For Silicide Etching

We have developed a decoupled plasma source (DPS) etcher for polysilicon and polycide etching. A series of experiments has been carried out to study polycide gate etching in the DPS etcher. By combining conventional techniques of process evaluation with in situ monitoring of ions and radical chemistry and with real-time ion flux density distribution measurements, we quantitatively determined trends in polycide processing and etching with simple Cl2 and He/O2 chemistry. Performance parameters, such as etch rate, etch rate microloading, etch rate uniformity, profile, profile microloading and profile uniformity on WSix , oxide, polysilicon and photoresist, were measured at 24 points on the surface matrix. These results were correlated with the physical and chemical parameters of the decoupled plasma, such as ion flux distribution, DC-bias potential across the wafer, plasma ion composition and concentration of neutrals. A vertical profile can be obtained with highly selective polycide etch in a single step main etch with Cl2 and He/O2 using a decoupled plasma silicon etch reactor.

Dual-polycide gate technology using regrowth amorphous-Si to suppress lateral dopant diffusion

Process techniques for dual-polycide gate CMOS have been developed. The origin of lateral dopant diffusion is analyzed, and an enlarged-grain dual-polycide gate technology using regrowth amorphous-Si (a-Si) is proposed. Reduction of the dopant absorption into the silicide layer has been observed in the regrowth of a-Si polycide gate structure. Lateral dopant diffusion has been suppressed to less than 0.1 /spl mu/m, and, as a result, 0.2 /spl mu/m n-MOS/p-MOS spacing has been realized under an 850/spl deg/C furnace annealing process. This technology can also achieve current drivability improvement by suppressing the gate depletion simultaneously. Suppression of boron penetration through the gate oxide to the channel region from the p/sup +/ gate has been realized by gate doping ion implantation into the a-Si, and no threshold voltage lowering with small standard deviation has been confirmed. It has been recognized that the above techniques are a possible solution for the dual-polycide gate CMOS structure.

Hot-carrier induced degradation of polysilicon and tungsten polycide gate MOSFETs under maximum substrate and gate current stresses

Under maximum substrate current stress (i.e. ), the hot-carrier induced degradation of tungsten polycide gate n-MOSFETs in the linear drain current and maximum linear transconductance is lower, and the shift in the threshold voltage is higher than that of polysilicon gate (PolySi) n-MOSFETs. However, under maximum gate current stress (i.e. ), the n-MOSFETs showed higher hot-carrier induced degradation than the PolySi devices. In contrast, p-MOSFETs showed higher degradation compared with the PolySi p-MOSFETs under both (i.e. ) and (i.e. ) stresses. An explanation, substantiated by charge-pumping measurements, is proposed to explain the phenomena observed. The hot-carrier lifetime of p-MOSFETs is found to limit the operation of CMOS circuits.

Device characteristics of a 30-V-class thin-film SOI power MOSFET

A 30-V thin-film SOI power MOSFET having a tungsten polycide gate with a linear gate topology has been fabricated at a practical device level. Its electrical characteristics were successfully demonstrated for the first time. The experimental device has 1010 unit cells and a total gate width of 4.04 cm, It has a specific on-resistance of 92 m/spl Omega//spl middot/mm/sup 2/ and breakdown voltage of 33 V. The device's various parasitic capacitance characteristics were measured and compared with those of a lateral power MOSFET fabricated on a bulk-silicon substrate.

Advanced metallization technology for 256M DRAM

An advanced three-level interconnect technology for 0.25 μm design rule has been developed for a 256M DRAM process, that provides increased circuit density, improved manufacturability and reduced cost. The process includes a polycide gate stack, self-aligned bitline contacts, a tungsten bitline, an Al-stitched wordline for the second level of metal and an Al global wiring level. Chemical-mechanical polishing (CMP) has been extensively used to improve planarity which increases the process window for lithography and etch. This metallization concept has been implemented on a 256M DRAM within the framework of a process architecture including a BuriEd STrap (BEST) trench memory cell and shallow trench isolation (STI). Five novel processes are discussed in detail. A self-aligned array contact using a highly selective etch process for SiO 2 Si 3N 4 , low ∈ IMD of fluorosilicate glass (FSG) deposited in a dual-frequency plasma CVD process (D-FSG) in comparison to HDP CVD and an alternative low-cost monolithic stud-wire concept using high temperature Al-PVD and planarization by a non-corrosive Al CMP. The “Dual Damascene” interconnects show improved electromigration resistance compared to RIE-patterned Al-sandwich structures on W studs.

A comparison of C54-TiSi2 formation in blanket and submicron gate structures using in situ x-ray diffraction during rapid thermal annealing

We demonstrate the use of a synchrotron radiation source for in situ x-ray diffraction analysis during rapid thermal annealing (RTA) of 0.35 μm Salicide (self-aligned silicide) and 0.4 μm Polycide (silicided polysilicon) TiSi2 Complementary Metal Oxide Semiconductor (CMOS) gate structures. It is shown that the transformation from the C49 to C54 phase of TiSi2 occurs at higher temperatures in submicron gate structures than in unpatterned blanket films. In addition, the C54 that forms in submicron structures is (040) oriented, while the C54 that forms in unpatterned Salicide films is randomly oriented. Although the preferred oreintation of the initial C49 phase was different in the Salicide and Polycide gate structures, the final orientation of the C54 phase formed was the same. An incomplete conversion of C49 into C54-TiSi2 during the RTA of Polycide gate structures was observed and is attributed to the retarding effects of phosphorus on the transition.

A polycide gate electrode with a conductive diffusion barrier formed with ECR nitrogen plasma for dual gate CMOS

A simple diffusion barrier technology for polycide gate electrodes is presented. An extremely thin silicon nitride layer is formed by poly Si surface nitridation with ECR nitrogen plasma of only nitrogen gas and without substrate heating. The silicon nitride layer acts as an excellent barrier to impurity diffusion from polysilicon to silicide. It was found that barrier formation with ECR nitrogen plasma results in no fatal degradation in the MOS interface characteristics. This technology is very effective for making dual polycide gates inexpensively due to its simplicity and a good affinity with conventional ULSI fabrication processes.