Effects of the Process Variable on Sputtered TiSix Polycide Gate Electrodes for sub-0.15 μm Memory Device Application

Abstract

We examine effects of the process variables of transistor gate structures on material and electrical properties of films and patterned polycide gate lines at sub-0.15 μm regime. The process variables include molar ratio of Si/Ti in composite targets 2.2, 2.3, and 2.4), sputter deposition temperature, film thickness, rapid thermal annealing (RTA) process condition, and postannealing in a furnace. At high Si precipitate formation is highly pronounced at the film surface as RTA temperature increases and contributes to the increase in surface roughness of the films. Moreover, processes of higher x targets show a greater number of add-on particles and more retarded phase transformation. The RTA process after film deposition completely transforms films to phase even at very fine lines when annealed at 800°C or higher for 20 s. The maximum thermal budget allowed for postannealing is 800°C for 60 min, where no appreciable thermal degradation is shown in bar resistance regardless of target composition. At this postannealing condition, excellent bar resistance (∼4.4 Ω/□) and thermal stability are shown at 0.12 μm linewidth when films were sputtered at 200°C. films sputtered at 500°C show a stronger (040) C54 preferred orientation and greater degraded thermal stability than the films deposited at 200°C, and exhibit a bar resistance of ∼5 Ω/□ at 0.12 μm linewidth. © 2001 The Electrochemical Society. All rights reserved.