Abstract
Process techniques for dual-polycide gate CMOS have been developed. The origin of lateral dopant diffusion is analyzed, and an enlarged-grain dual-polycide gate technology using regrowth amorphous-Si (a-Si) is proposed. Reduction of the dopant absorption into the silicide layer has been observed in the regrowth of a-Si polycide gate structure. Lateral dopant diffusion has been suppressed to less than 0.1 /spl mu/m, and, as a result, 0.2 /spl mu/m n-MOS/p-MOS spacing has been realized under an 850/spl deg/C furnace annealing process. This technology can also achieve current drivability improvement by suppressing the gate depletion simultaneously. Suppression of boron penetration through the gate oxide to the channel region from the p/sup +/ gate has been realized by gate doping ion implantation into the a-Si, and no threshold voltage lowering with small standard deviation has been confirmed. It has been recognized that the above techniques are a possible solution for the dual-polycide gate CMOS structure.
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