poly-Si Thin Film Research Articles

ナノ加工による多結晶シリコン薄膜の熱電変換能の増強

ナノ加工による多結晶シリコン薄膜の熱電変換能の増強

Charge-trap non-volatile memories fabricated by laser-enabled low-thermal budget processes

We fabricated charge-trap non-volatile memories (NVMs) using low thermal budget processes, including laser-crystallization of poly-Si thin film, chemical vapor deposition deposition of a stacked memory layer, and far-infrared-laser dopant activation. The thin poly-Si channel has a low defect-density at the interface with the bulk, resulting in a steep subthreshold swing for the NVM transistors. The introduction of the stacked SiO2/AlOxNy tunnel layer and the SiNx charge-trap layer with a gradient bandgap leads to reliable retention and endurance at low voltage for the NVMs. The low thermal budget processes are desirable for the integration of the nano-scaled NVMs into system on panels.

Dopant transfer from poly-si thin films to c-Si: An alternative technique for device processing

An alternative technique for production of devices which uses both silicon crystalline wafers (p-type) and heavy doped amorphous silicon thin films (n-type) is reported. The amorphous silicon acts as a finite source of dopant and is deposited (at low temperature, 70°C) by plasma enhanced chemical vapor deposition on silicon wafers. Afterwards, the process of dopant diffusion into the crystalline silicon occurs in a diffusion furnace at 1000°C for 2h, to create p–n junctions. Using SIMS analyses, a dopant (P) transfer into c-Si of about 30% is verified and 87% of the dopant transferred is electrically active. Consequently, n-MOSFET devices are produced using a gate oxide thermally grown at the same diffusion temperature for one hour. The preliminary results of the MOSFET (channel length and width of 0.5 and 5mm, respectively) show a depletion behavior with a threshold voltage, Vth=−8.2V and afield-effect mobility, µFE=187.8cm2/(Vs).

Characteristics of Polycrystalline Si Thin Film—Solid Solubility and Mobility Study

Carrier solid solubility (SS) and mobility of polycrystalline silicon (poly-Si) thin film as the functions of the doping ion species and annealing conditions (temperature and time) are characterized. The study of SS and mobility shows that the poly-Si thin film has lower chemical SS and electrically active SS and much lower mobility ( $\mu$ ) than a single-crystalline Si substrate, because polygrain boundaries dominate carrier scattering mechanism. For the poly-Si thin film, doping ion species show relatively less impact on SS and mobility data, but annealing thermal budgets (temperature and time) show more impact on SS and mobility data.

Effects of Channel Width on High-Frequency Characteristics of Trigate Poly-Si Thin-Film Transistors Fabricated by Microwave Annealing

In this paper, the high-frequency performance of trigate polycrystalline silicon thin-film transistors (poly-Si TFTs) is analyzed using low-temperature microwave annealing. The variation of the cutoff frequency and the maximum oscillation frequency with the width of the channel wire is investigated. A poly-Si TFT with a short channel and a narrow channel wire, annealed using microwave, has a high driving current, a good gate controllability, and a better high-frequency performance than one that annealed by rapid thermal annealing.

Ultra Large-Grain Poly-Si Thin-Film Transistor Using NiSi<sub>2</sub> Seeding Si-Amplified Layer

A novel technique for enlarging grains of poly-Si thin-film has been successfully demonstrated, using a 1-μm thick Si-amplified layer (SAL) and NiSi <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> seeds on the top. It was applied to top-gated thin-film transistors (TFTs) and showed high electrical performance. The NiSi <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> seeds induce vertical crystallization in the SAL and migrate toward the bottom, forming columnar grains. The grain size of the poly-Si thin-film increases when the NiSi <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> seeds diffuse deeply into the SAL and eventually an ultralarge-grain (ULG) poly-Si thin film is formed. The SAL was removed for use in the fabrication of a top-gated TFT. The performance of the ULG poly-Si TFT was compared with that of a NiSi <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> seed-induced crystallized poly-Si TFT which was fabricated without an SAL.

(Invited) High-Performance Top-Gate and Double-Gate Low-Temperature Polycrystalline-Silicon Thin-Film Transistors Fabricated Using Continuous-Wave-Laser Lateral Crystallization on a Glass Substrate

A high-quality polycrystalline silicon (poly-Si) film is a technology for improving the performance of low-temperature (LT) poly-Si thin-film transistors (TFTs). We have already developed continuous-wave-laser lateral crystallization (CLC) using a diode-pumped solid-state laser to improve the crystalline quality of the thin poly-Si film. In this paper, we report on two approaches for improving the performance of LT poly-Si TFTs, which are based on a thin CLC poly-Si film and are fabricated at 550 ºC on a glass substrate. The first approach is a combination of a CLC poly-Si film and sputtered HfO2 as the gate dielectric. The other approach is a combination of a CLC poly-Si film and a double-gate structure for realizing four-terminal LT poly-Si TFTs. The former exhibited an enhancement in the on-current that was four times greater than a device with a silicon dioxide gate stack. In the latter, high controllability of the threshold voltage was confirmed.

Crystallization of a-Si films with smooth surfaces by using Blue Multi-Laser Diode Annealing

Crystallization of ∼50-nm-thick amorphous Si (a-Si) with a smooth surface was achieved by using Blue Multi-Laser Diode Annealing (BLDA). The a-Si films were deposited by using RF sputtering with Ne gas or by using plasma enhanced chemical vapor deposition (PE-CVD) and were annealed by using BLDA with CW scanning. After the films had been annealed a relatively low laser power below 4 W, the root-mean-square (RMS) roughness deduced from the atomic force microscopy (AFM) results for the surfaces of the Si films was slightly increased, but smoothness was within 3 nm despite the conditions under which the films had been crystallized. BLDA has a potential to realize next-generation poly-Si thin film transistors (TFTs).

High-Frequency Performance of Trigate Poly-Si Thin-Film Transistors by Microwave Annealing

This letter investigates the high-frequency performance of trigate polycrystalline silicon thin-film transistors (poly-Si TFTs) using low temperature microwave annealing (MWA). MWA exhibits sufficient dopant activation efficiency, good short channel effect control, and a higher maximum oscillation frequency (f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> ) of poly-Si TFTs than does rapid thermal annealing. In addition, MWA can fabricate nanoscale devices. Poly-Si TFTs with short channel annealed by microwave reveals better high-frequency performance and switching characteristics.

A Novel Design of Quasi-Lightly Doped Drain Poly-Si Thin-Film Transistors for Suppression of Kink and Gate-Induced Drain Leakage Current

An ultrathin channel of poly-Si thin-film transistors with a quasi-lightly doped drain (Q-LDD) structure, which reduces the kink current considerably, have been proposed and fabricated. The doping concentration on the poly-Si channel was adjusted by the different thickness between source-drain and LDD region. The proposed Q-LDD shows advantages of using a thin channel and a thin-gate insulator, comparing with the conventional fabrication process of LDD using a thick oxide side walls. The gate-induced drain leakage currents were successfully suppressed without sacrifice of the ON-current and threshold voltage. Moreover, the kink effect also reduced.

Controlling Stress in Large-Grained Solid Phase Crystallized n-Type Poly-Si Thin Films To Improve Crystal Quality

High-quality n-type solid-phase crystallized (SPC) polycrystalline silicon thin films are successfully made on planar glass by controlling the stress and intragrain misorientation in the films. If not controlled, the stress in the films is found to exceed 650 MPa, with a high intragrain misorientation of up to 5°. The stress is successfully engineered to values below 130 MPa through the control of the a-Si:H deposition temperature and the PH3 (2% in H2)/SiH4 gas flow ratio. The stress and intragrain misorientations in the SPC poly-Si films are found to affect their crystal quality. The poly-Si thin films with the best crystal quality are also found to have the least tensile stress and a low intragrain misorientation of about 1°. The effects of the PH3 (2% in H2)/SiH4 gas flow ratio and the a-Si:H deposition temperature on the material quality of the n-type SPC poly-Si thin films are systematically investigated using Raman microscopy and electron backscatter diffraction.

Investigating the effects of microstructure on optical properties of different kinds of polysilicon thin films

Abstract Flat, B-doped, low-stress and non-stress polysilicon (poly-Si) thin films were deposited by low pressure chemical vapor deposition (LPCVD). X-ray diffraction (XRD), combined with atomic force microscopy (AFM) and Raman system, UV-Raman measurements and spectroscopic ellipsometry, was used to study the microstructure, the morphology and optical properties of the films. The results indicate that the surface roughness is related to the grain size and the change in the microstructure. The B-doped poly-Si shows a tensile stress, while the flat poly-Si shows a high compressive stress. The bandgap of the B-doped poly-Si is the narrowest because of its most disordered microstructure.

Effect of hydrogen on low temperature epitaxial growth of polycrystalline silicon by hot wire chemical vapor deposition

Polycrystalline silicon (poly-Si) films were prepared by hot-wire chemical vapor deposition (HWCVD) at a low substrate temperature of 525 °C. The influence of hydrogen on the epitaxial growth of ploy-Si films was investigated. Raman spectra show that the poly-Si films are fully crystallized at 525 °C with a different hydrogen dilution ratio (50%–91.7%). X-ray diffraction, grazing incidence X-ray diffraction and SEM images show that the poly-Si thin films present (100) preferred orientation on (100) c-Si substrate in the high hydrogen dilution condition. The P-type poly-Si film prepared with a hydrogen dilution ratio of 91.7% shows a hall mobility of 8.78 cm2/(V·s) with a carrier concentration of 1.3 × 1020 cm−3, which indicates that the epitaxial poly-Si film prepared by HWCVD has the possibility to be used in photovoltaic and TFT devices.

Approximate analytical channel potential model of poly-Si thin film transistors operated in the strong inversion region under the high gate and low drain biases

An approximate analytical channel potential model of polycrystalline silicon thin film transistors operated in the strong inversion region under the high gate and low drain biases is proposed. Thus, the linear relationship between the channel potential and the drain voltage is derived in the strong inversion region under the above bias condition when the polysilicon layer is ultrathin. This model agrees with the two-dimensional-device simulation results under different gate voltages, different drain voltages and different channel lengths. By comparing the relative errors between the model and the simulation results, it presents that this model is more suitable under the higher gate voltage Vg or the lower drain voltage Vd, regardless of the channel length. And this approximate analytical model is helpful in solving the two- dimensional-device problem by one-dimensional Poisson's equation since the drain bias is taken into account in the channel potential.

Impact of deposition parameters on the material quality of SPC poly-Si thin films using high-rate PECVD of a-Si:H

The impact of the deposition parameters such as gas flow (sccm) and RF plasma power density (W/cm2) on the deposition rate of a-Si:H films is systematically investigated. A high deposition rate of up to 146 nm/min at 13.56 MHz is achieved for the a-Si:H films deposited with high lateral uniformity on 30 × 40 cm2 large-area glass substrates. A relationship between the SiH4 gas flow and the RF power density is established. The SiH4 gas flow to RF power density ratio of about 2.4 sccm/mW cm-2 is found to give a linear increase in the deposition rate. The influence of the deposition rate on the material quality is studied using UV-VIS-NIR spectrophotometer and Raman characterisation techniques. Poly-Si thin film with crystal quality as high as 90% of single-crystalline Si wafer is obtained from the SPC of high rate deposited a-Si:H films.

Self-aligned offset gate poly-Si TFTs using photoresist trimming technology

This paper reports a simple method of fabricating self-aligned offset gate (SAOG) polycrystalline silicon (poly-Si) thin film transistors (TFTs). The SAOG structure was formed by two key steps, i.e. an isotropic photoresist trimming and an additional gate fringe etching. The fabricated SAOG devices with this proposed method exhibit a significantly suppressed off-current increase with gate bias compared with the non-offset ones, and have identical bi-directional transfer characteristics under reversed source/drain biases. It is also shown that the performances of poly-Si TFTs with metal-induced lateral crystallization can be improved significantly by annealing in forming gas.

Synthesis and characterization of large-grain solid-phase crystallized polycrystalline silicon thin films

n-type polycrystalline silicon (poly-Si) films with very large grains, exceeding 30 μm in width, and with high Hall mobility of about 71.5 cm2/V s are successfully prepared by the solid-phase crystallization technique on glass through the control of the PH3 (2% in H2)/SiH4 gas flow ratio. The effect of this gas flow ratio on the electronic and structural quality of the n-type poly-Si thin film is systematically investigated using Hall effect measurements, Raman microscopy, and electron backscatter diffraction (EBSD), respectively. The poly-Si grains are found to be randomly oriented, whereby the average area weighted grain size is found to increase from 4.3 to 18 μm with increase of the PH3 (2% in H2)/SiH4 gas flow ratio. The stress in the poly-Si thin films is found to increase above 900 MPa when the PH3 (2% in H2)/SiH4 gas flow ratio is increased from 0.025 to 0.45. Finally, high-resolution transmission electron microscopy, high angle annular dark field-scanning tunneling microscopy, and EBSD are used to identify the defects and dislocations caused by the stress in the fabricated poly-Si films.

Fabrication of a high-performance poly-Si thin-film transistor using a poly-Si film prepared by silicide-enhanced rapid thermal annealing process

A 50-nm thick polycrystalline Si film was fabricated by the crystallization of anamorphous Si film using silicide-enhanced rapid thermal annealing (SERTA). The amorphous Si film was deposited on a 5-nm thick polycrystalline Si seed layer containing nickel silicide precipitates in grain boundary areas. With the help of the silicide precipitates, the RTA temperature decreased from 730 to 680°C and the grain size of the crystallized polycrystalline Si film increased to 1.4 — 2.2 μm. Few defects were found within the grains and the Ni concentration in the polycrystalline film decreased to 1 × 1018 cm−3 due to the very-thin seed layer that contained nickel silicide precipitates. As a result, the field-effect hole mobility in the p-channel poly-Si thin film transistors (TFTs), fabricated employing the polycrystalline Si film, was as high as 169 cm2/V∙s at a drain voltage of V D = −0.1 V; the subthreshold swing was as small as 0.24 V/decade. The minimum leakage current at V D = 5V was 1.5 × 10−10 A with very good diode characteristics.

ANNEALING OF POLYCRYSTALLINE THIN FILM SILICON SOLAR CELLS IN WATER VAPOUR AT SUB-ATMOSPHERIC PRESSURES

Thin film polycrystalline silicon (poly-Si) solar cells were annealed in water vapour at pressures below atmospheric pressure. PN junction of the sample was contacted by measuring probes directly in the pressure chamber filled with steam during passivation. Suns-VOC method and a Lock-in detector were used to monitor an effect of water vapour to VOC of the solar cell during whole passivation process (in-situ). Tested temperature of the sample (55°C – 110°C) was constant during the procedure. Open-circuit voltage of a solar cell at these temperatures is lower than at room temperature. Nevertheless, voltage response of the solar cell to the light flash used during Suns-VOC measurements was good observable. Temperature dependences for multicrystalline wafer-based and polycrystalline thin film solar cells were measured and compared. While no significant improvement of thin film poly-Si solar cell parameters by annealing in water vapour at under-atmospheric pressures was observed up to now, in-situ observation proved required sensitivity to changing VOC at elevated temperatures during the process.

Fabrication of high performance thin-film transistors via pressure-induced nucleation.

We report a method to improve the performance of polycrystalline Si (poly-Si) thin-film transistors (TFTs) via pressure-induced nucleation (PIN). During the PIN process, spatial variation in the local solidification temperature occurs because of a non-uniform pressure distribution during laser irradiation of the amorphous Si layer, which is capped with an SiO2 layer. This leads to a four-fold increase in the grain size of the poly-Si thin-films formed using the PIN process, compared with those formed using conventional excimer laser annealing. We find that thin films with optimal electrical properties can be achieved with a reduction in the number of laser irradiations from 20 to 6, as well as the preservation of the interface between the poly-Si and the SiO2 gate insulator. This interface preservation becomes possible to remove the cleaning process prior to gate insulator deposition, and we report devices with a field-effect mobility greater than 160 cm2/Vs.