Planarization Of Wafers Research Articles

Double-Oxidant-Induced Slurry Reaction Mechanism and Performance on Chemical Mechanical Polishing of 4H-SiC (0001) Wafer.

Single-oxidant slurries are prevalently utilized in chemical and mechanical polishing (CMP) of 4H-SiC crystal. Nevertheless, it is a challenge to achieve a high material removal rate (MRR) and surface quality using single oxidant slurries to meet the needs of global planarization and damage-free nanoscale surface processing of SiC wafers. To solve this challenge, a novel method is proposed for SiC CMP processing using the double oxidant slurry. This slurry mainly consists of alumina (Al2O3) abrasive particles, potassium permanganate (KMnO4), potassium persulfate (K2S2O8), and deionized water. Post CMP, MRR is 1045 nm/h calculated by scratch method, and surface roughness Sa is 0.33 nm measured by 3D optical surface morphometer, with the measurement area of 868 μm × 868 μm. Both the MRR and Sa are far better than those under the single oxidant slurry condition. CMP mechanism with double-oxidant slurry conditions is elucidated by energy dispersive spectrometer and X-ray photoelectron spectrometer. Initially, the Si-C bond on the SiC wafer surface was oxidized by KMnO4, then MnO2 as the reduction product of KMnO4 can also catalyze the S2O82- to further oxidize SiC wafer surface, and eventually the oxidation layers were removed by mechanical action of nano-Al2O3 abrasive particles during CMP processing. These findings offer a pioneering approach and novel perspectives to achieve a higher MRR of 4H-SiC CMP, with potential implications for the application in high-performance SiC devices.

A Novel Contactless SiC Wafer Planarization Processing after Mechanical Slicing by Dynamic Thermal Annealing Processes

In conventional machining of SiC wafers, material loss and sub-surface damage (SSD) of both the front and back surfaces are major issues. In this study, we focused on Dynamic AGE-ing® (DA), which is a sublimation-controlled process, and applied it to the total wafering process without any mechanical contact of both the front and back surfaces to explore the possibilities to reach the CMP-equivalent quality. DA process enables material lossless planarization of SiC wafers by applying a temperature gradient to achieve simultaneous etching and growth at the same rate on one and the other surfaces, respectively. To drive the planarization function for a multi-wire saw finished as-sliced wafer, as an example, a high-temperature regime above 2000 °C under an Ar background pressure higher than 1 kPa to suppress etching and growth rates was employed as the first step in the DA treatment. In this step, an effective annealing function arises where sublimation and recrystallization occur simultaneously through a sub-surface region on both sides of the wafer. Due to the active interchange of the surface and subsurface layer, a self-organizing planarization effect occurs on a macroscopic scale on both surfaces with the removal of SSD. The conventional DA processes were employed for the following microscopic flatness control. As a result, the roughness of the 6-inch as-sliced wafer was reduced to 0.7 nm on the Si-face and 2.0 nm on the C-face while maintaining the wafer thickness. This is the first promising result exhibiting the potential of thermal contactless treatment for next-generation wafer manufacturing by improving quality and cost.

Development of rigid polishing materials for use in microelectronics

The paper presents the results of development of conditions for obtaining hard polishing materials based on polyetherurethane solutions for chemical-mechanical planarization of semiconductor silicon wafers.

Virtual metrology for chemical mechanical planarization of semiconductor wafers

Virtual metrology for chemical mechanical planarization of semiconductor wafers

MD simulation of chemically enhanced polishing of 6H-SiC in aqueous H2O2

Chemical enhanced polishing (CEP) is a widely employed final process for achieving precise surface shaping and planarization of semiconductor wafers. However, determining the chemical effect involved in material removal through experimental means is extremely challenging. In this study, we conducted reactive force field (ReaxFF) molecular dynamics (MD) simulations to gain insight into the chemical effects of CEP using an aqueous hydrogen peroxide (H2O2) diamond suspension as a polishing medium for 6H-SiC single crystals. The inclusion of aqueous H2O2 resulted in the formation of SiOH and COH species, which are comparatively easier to remove through mechanical abrasion. Furthermore, an increase in H2O2 concentration was found to enhance the material removal. The MD simulations also revealed that the chemical effects on the Si-face of 6H-SiC were more pronounced than those on the C-face due to the generation of a greater number of SiO species and the favourable atomic structure of the Si-face for chemical removal. The results showed that the material remove rate on the Si-face is greater than that on the C-face during polishing, aligning with the findings from MD simulation. Furthermore, a systematic experimental study was carried out to examine the influence of various conditions on material removal rate and surface quality in both polishing and lapping processes.

Development of elastic polishing materials for the process of chemical-mechanical planarization

The paper presents the results of the development of conditions for the production of elastic polishing materials based on solutions of polyethyruretanes, for the chemical-mechanical planarization of semiconductor silicon wafers.

Vibration Signal-Assisted Endpoint Detection for Long-Stretch, Ultraprecision Polishing Processes

AbstractThe research reported in this article is concerned with the question of detecting and subsequently determining the endpoint in a long-stretch, ultraprecision surface polishing process. While polishing endpoint detection has attracted much attention for several decades in the chemical-mechanical planarization of semiconductor wafer polishing processes, the uniqueness of the surface polishing process under our investigation calls for novel solutions. To tackle the research challenges, we develop both an offline model and an online detection method. The offline model is a functional regression that relates the vibration signals to the surface roughness, whereas the online procedure is a change-point detection method that detects the energy turning points in the vibration signals. Our study reveals a number of insights. The offline functional regression model shows clearly that the polishing process progresses in three states, including a saturation phase, over which the polishing action could be substantially shortened. The online detection method signals in real-time when to break a polishing cycle and to institute a follow-up inspection, rather than letting the machine engage in an overpolishing cycle for too long. When implemented properly, both sets of insights and the corresponding methods could lead to substantial savings in polishing time and energy and significantly improve the throughput of such polishing processes without inadvertently affecting the quality of the final polish.

Monodisperse colloidal silica with excellent batch-to-batch reproducibility by stoichiometric seeded growth strategy

Monodisperse colloidal silica have been extensively used as models for inter-particle interaction investigation, standards for instrument calibration and polishing agents for global planarization of wafer in integrated circuit manufacturing. Despite marvelous achievements made for colloidal silica synthesis in the past decades, a long-standing challenge for massive production of colloidal silica lies in the batch-to-batch reproducibility. Herein, we present a stoichiometric seeded growth strategy for the massive production of monodisperse colloidal silica, where the silica precursors are designed to exclusively condense on the surface of seed particles with single Q4 Si species, enabling a precise control of resultant colloidal silica size by the feeding precursor/seed ratios, and consequently, achieving excellent batch-to-batch reproducibility. Governed by the stoichiometric correlation, customized size of colloidal silica at high precision (∼1 nm in diameter) can be prepared in large quantity. More importantly, this seeded growth strategy has rather high tolerance on the size distribution of seed particles; monodisperse colloidal silica can be readily obtained from even polydisperse seed particles, significantly lowing the cost of monodisperse particles, therefore, highlighting the feasibility of large-scale application of monodisperse colloidal silica.

Hydrogen etching of 4H–SiC(0001) facet and step formation

SiC has attracted much interest due to its vast applications in high power, high frequency and radiation-hardened electronics at high temperatures. Although the growth and processing technology for SiC wafers has matured, scratches created during surface preparation will unavoidably deteriorate both device performances and the quality of materials which are fabricated on it. Hydrogen etching has been proposed as an effective approach to obtain ideal SiC surfaces with large atomically flat steps. Here, we reported a systematical investigation on the effects of processing parameters to the hydrogen etching of 4H–SiC (0001). Accordingly, a new two-step etching method was developed with a specifically designed crucible to take advantage of the found correlation between those parameters and the terrace features. The method demonstrates high efficiency to realize atomically uniform SiC surface morphology with more than 70% coverage of the sample surface. It offers a possible route for large scale industrial SiC wafer planarization.

Grinding and lapping induced surface integrity of silicon wafers and its effect on chemical mechanical polishing

Grinding and lapping are two widely used machining processes for silicon wafer planarization. Their resultant surface integrity has a significant impact on subsequent polishing and hence the overall manufacturing cost. In this work, the morphologies and damage patterns of the ground and lapped silicon surfaces were comparatively investigated and the effect of surface integrity on subsequent chemical mechanical polishing (CMP) was understood. In the regime of ductile removal, the ground silicon surface had regularly distributed striations, but the lapped surface consisted of randomly and homogeneously distributed scratches. The lapped surface had a softer damage layer than the ground one because more stacking faults were induced in the silicon sublayer. In the subsequent process of CMP, the roughness of the lapped surface was decreased faster, but its corresponding material removal rate (MRR) was lower, in comparison to the CMP of the ground surface with the same starting roughness value. A bearing area ratio model was developed to elucidate the removal mechanism involved in polishing. The lapped surface was found to have a higher bearing area ratio than the ground, indicating that a larger surface area was removed, thus leading to a lower MRR.

SiC Mass Commercialization: Present Status and Barriers to Overcome

In an increasingly electrified technology driven world, power electronics is central to the entire clean energy manufacturing economy. Silicon (Si) power devices have dominated power electronics due to their low cost volume production, excellent starting material quality, ease of fabrication, and proven reliability. Although Si power devices continue to improve, they are approaching their operational limits primarily due to their relatively low bandgap, critical electric field, and thermal conductivity that result in high conduction and switching losses, and poor high temperature performance. Silicon Carbide’s (SiC) compelling efficiency and system benefits have led to significant development efforts over the last two decades and today planar and trench MOSFETs, and JFETs are commercially available from several vendors as discrete components or in high power modules in the of 650 V to 1700 V voltage range. High impact application opportunities, where SiC devices are displacing their incumbent Si counterparts, have emerged and include automotive and rail power electronics with reduced losses and reduced cooling requirements; novel data center topologies with reduced cooling loads and higher efficiencies; variable frequency drives for efficient high power electric motors at reduced overall system cost; more efficient, flexible, and reliable grid applications with reduced system footprint; and “more electric aerospace” with weight, volume, and cooling system reductions contributing to energy savings. In particular, SiC insertion in electric vehicles brings major competitive advantages and is a volume application opportunity that can spur manufacturing economies of scale and lower system costs. As SiC continues to grow, the industry is lifting the last barriers to mass commercialization that include higher than Si device cost, relative lack of wafer planarity, the presence of basal plane dislocations, reliability and ruggedness concerns, and the need for a workforce skilled in SiC power technology to keep up with the rising demand. It should be noted that in many applications, insertion of SiC reduces overall system cost compared to Si even though SiC devices can cost 2-3 more than their Si counterparts. This is due to the passive component and cooling system simplifications enabled by the efficient high frequency SiC operation. In this paper, we will review key aspects of SiC technology and discuss overcoming barriers to mass commercialization.

Three-dimensional curving of crystal planes in wide bandgap semiconductor wafers visualized using a laboratory X-ray diffractometer

The curving of crystal planes (CCP) in wide bandgap semiconductor wafers, caused by thermal stress during crystal growth or wafer planarization processes, poses serious problems in subsequent epitaxial growth and device fabrication; therefore, it requires a precise assessment. In this paper, we report a method for visualizing the CCP in three-dimensional space using a laboratory X-ray diffractometer. The characteristic CCP is presented for 4H-SiC, GaN, AlN, and β-Ga2O3 commercial substrates with widely varied size and thickness, surface orientation, surface treatment, dopant species, and dislocation density. The results will aid crystal growers in gaining an overview regarding the shape of the CCP (e.g., convex or concave, isotropic or anisotropic) and the radius of curvature in these up-to-date power semiconductor wafers. The method can be used to optimize crystal growth conditions and wafer planarization processes.

In Situ Metrology for Pad Surface Monitoring in CMP Using a Common-Path Phase-Shifting Interferometry: A Feasibility Study

In the fabrication of semiconductors, chemical mechanical polishing (CMP) is an essential wafer-planarization process. For optimal CMP, it is crucial to monitor the texture of the polishing pad; this leads to homogenous planarization of wafers. Hence, we present a new interferometric approach for in situ evaluation of the CMP pad surface based on a common-path phase-shifting interferometry, with which a series of phase-modulated interference signals immune to external perturbation can be recorded. A nanoscopic surface topology can then be reconstructed to estimate surface roughness using the recorded interference images. The surface mapping performance of the proposed method was tested by retrieving a topology of a vibrating nanostructure in immersion, of which height profiles were consistent with the result from atomic force microscopy (AFM). The method was also validated by examining the surface of a used CMP pad in simulated conditions.

Analysis on Pad Surface Roughness of Diamond Conditioning Process for CMP

Chemical Mechanical Polishing/Planarization (CMP) is the key process of the wafer and thin film planarization process for semiconductor manufacturing. In the CMP process, the pad can restore its surface topography and efficiency by diamond conditioner or named as diamond conditioning process. The pad surface roughness is essential to the removal rate in the CMP process because it can represent the contact level of the polishing pad and wafer. This study has developed a simulation program based on precise diamond-grits conditioning routes and numbers of cross points. By studying the OP (overlap cutting points) distribution in a specific area on the pad which is generated by CL (cutting locus), the trend of roughness parameters is discovered. The simulation and experimental model can be effective to observe pores deformation and predict pad surface topography. The results show the pad roughness would become steady over a certain OP number, and the OP can be precisely calculated and compared to the actual pad surface. The final results of the break-in and pad conditioning process can be estimated or further optimized. The other high-density and customized diamond-grits arrangement of conditioner can be designed according to the study in future work.

Wafer Level Packaging Technology Applied to Pixel Detectors

Pixel technology is commonly used in the tracking systems of High Energy Physics detectors with physical areas that have largely increased in the last decades. To ease the production of several square meters of sensitive area, the possibility of using the industrial Wafer Level Packaging to reassemble good single sensor tiles from multiple wafers into a reconstructed full wafer is investigated. This process reconstructs wafers by compression molding using silicon charged epoxy resin. We tested high glass transition temperature low-stress epoxy resins filled with silica particles to best match the thermal expansion of the silicon die. These resins are developed and characterized for industrial processes, designed specifically for fan-out wafer-level package and panel-level packaging. In order to be compatible with wafer processing during the hybridization of the pixel detectors, such as the bump-bonding, the reconstructed wafer must respect challenging technical requirements. Wafer planarity, tile positioning accuracy, and overall thickness are amongst the main ones. In this paper the description of the process is given and preliminary results on a few reconstructed wafers using dummy tiles are reported. Strategies for Wafer Level Packaging improvements are discussed together with future applications to 3D sensors or CMOS pixel detectors.

Optimal design and experimental study of fixed abrasive pads based on coupling of damping regulation and pellet arrangement

Abstract. Lapping and polishing technology is an efficient processing method for wafer planarization processing. The structure of the fixed abrasive pad (FAP) is one of the most concerning issues in the research. The FAP structure affects the pressure distribution on the wafer surface, and the pressure distribution during processing has a significant influence on the wafer surface. Therefore, in this paper, a better pressure distribution is obtained by adjusting the angle of the spiral arrangement and the damping distribution of the damping layer of the FAP, thereby obtaining better processing quality. Based on the above theory, a new type of FAP, with coupling between the arrangement of the pellets and the damping regulation of the damping layer, was designed and optimized. The machining effects of different FAPs on the workpiece surface are compared in terms of material removal rate, material removal thickness, and surface roughness. The test results show that the workpiece material removal rate is higher than that of the traditional FAP when using the optimized FAP. The non-uniformity of the optimized FAP for that of material removal was 4.034 µm, which was lower than the traditional FAPs by 24.4 % and 17.6 %, respectively. The average surface roughness, Ra, of the optimized FAP is 0.21 µm, which is lower than 19.1 % and 12.5 % of the two traditional FAPs, respectively. Therefore, workpiece material removal and distribution are more uniform, and the surface quality of the workpiece is better when the optimized FAP processing is used. The test results prove that the optimized pellet arrangement and damping can achieve a better surface quality of the workpiece, which can meet the precision lapping process requirements for high-quality surfaces and large-scale production of brittle and hard materials such as sapphire.

Effects of Depth of Cutting on Damage Interferences during Double Scratching on Single Crystal SiC

In this work, the damage interference during scratching of single crystal silicon carbide (SiC) by two cone-shaped diamond grits was experimentally investigated and numerically analyzed by coupling the finite element method (FEM) and smoothed particle hydrodynamics (SPH), to reveal the interference mechanisms during the micron-scale removal of SiC at variable Z-axis spacing along the depth of cutting (DOC) direction. The simulation results were well verified by the scratching experiments. The damage interference mechanism of SiC during double scratching at micron-scale was found to be closely related to the material removal modes, and can be basically divided into three stages at different DOCs: combined interference of plastic and brittle removal in the case of less than 5 µm, interference of cracks propagation when DOC was increased to 5 µm, and weakened interference stage during the fracture of SiC in the case of greater than 5 µm. Hence, DOC was found to play a determinant role in the damage interference of scratched SiC by influencing the material removal mode. When SiC was removed in a combined brittle-plastic mode, the damage interference occurred mainly along the DOC direction; when SiC was removed in a brittle manner, the interference was mainly along the width of cutting; and more importantly, once the fragment of SiC was initiated, the interference was weakened and the effect on the actual material removal depth also reduces. Results obtained in this work are believed to have essential implications for the optimization of SiC wafer planarization process that is becoming increasingly important for the fabrication of modern electronic devices.

Removal Characteristics of Sapphire Lapping using Composite Plates with Consciously Patterned Resinoid-Bonded Semifixed Diamond Grits

Sapphire lapping is of key importance for the successful planarization of wafers that are widely present in electronic devices. However, the high hardness of sapphire makes it extremely challenging to improve its material removal rate during the lapping process without compromising surface quality and dimensional accuracy. In this work, a novel composite lapping plate consisting of a rigid resin frame and flexible sol–gel balls was fabricated with consciously designed patterns. Through lapping experiment, it was revealed that the diamond grits imbedded in the sol–gel balls can effectively lap the sapphire at a promising material removal rate (MRR), without the formation of undesirable scratches and loss of surface integrity. Moreover, by designing the arrangement patterns of sol–gel balls, the total thickness variation (TTV) can also be ensured for lapped sapphire substrates. The implications of experimental results were also discussed based on the trajectory analysis and contact mechanics of lapping grits in order to demonstrate the potential of the newly developed composite abrasive tools for sapphire-lapping applications.

Cytotoxicity Assessment of Gallium- and Indium-Based Nanoparticles Toward Human Bronchial Epithelial Cells Using an Impedance-Based Real-Time Cell Analyzer.

The semiconductor manufacturing sector plans to introduce III/V film structures (eg, gallium arsenide (GaAs), indium arsenide (InAs) onto silicon wafers due to their high electron mobility and low power consumption. Aqueous solutions generated during chemical and mechanical planarization of silicon wafers can contain a mixture of metal oxide nanoparticles (NPs) and soluble indium, gallium, and arsenic. In this work, the cytotoxicity induced by Ga- and In-based NPs (GaAs, InAs, Ga2O3, In2O3) and soluble III-V salts on human bronchial epithelial cells (16HBE14o-) was evaluated using a cell impedance real-time cell analysis (RTCA) system. The RTCA system provided inhibition data at different concentrations for multiple time points, for example, GaAs (25 mg/L) caused 60% inhibition after 8 hours of exposure and 100% growth inhibition after 24 hours. Direct testing of As(III) and As(V) demonstrated significant cytotoxicity with 50% growth inhibition concentrations after 16-hour exposure (IC50) of 2.4 and 4.5 mg/L, respectively. Cell signaling with rapid rise and decrease in signal was unique to arsenic cytotoxicity, a precursor of strong cytotoxicity over the longer term. In contrast with arsenic, soluble gallium(III) and indium(III) were less toxic. Whereas the oxide NPs caused low cytotoxicity, the arsenide compounds were highly inhibitory (IC50 of GaAs and InAs = 6.2 and 68 mg/L, respectively). Dissolution experiments over 7 days revealed that arsenic was fully leached from GaAs NPs, whereas only 10% of the arsenic was leached out of InAs NPs. These results indicate that the cytotoxicity of GaAs and InAs NPs is largely due to the dissolution of toxic arsenic species.

Effects of compound diamond slurry with graphene for lapping of sapphire wafers

Recently, sapphire has been used in a wide range of applications including optics, consumer electronics, and especially the rapidly growing LED wafer manufacturing. This paper investigates effects of a novel compound slurry composed of micron scaled diamond abrasives and various nano-platelets of graphene oxide (GO) for improving lapping performance of c-plane single-crystal aluminum oxide (Al2O3) sapphire wafers. Four kinds of graphenes including GO, reduced graphene oxide (RGO), ML-RGO (laminate), and MF-RGO (few-layer) are added into the diamond slurry to achieve compound slurries. Those compound slurries have been prepared with various graphene weight fractions in the range of 0.3 to 2.0 wt%, by LP (low power) or HP (high power) ultrasonication with different time spans in the range of 10 min to 48 h to adjust size of GOs. For the lapping process conducted by 10-min HP ultrasonicated GO (2.0 wt%)/diamond slurry, combination of medium down force pressure and the highest platen rotation speed of 45 kPa/80 rpm results in highest material removal rate (MRR) of 926.73 nm/min, which is 324% higher than MRR by pure diamond slurry. It is caused by high reactivity of GOs with sapphire wafer. As lapped at pressure/speed of 45 kPa/70 rpm by ultrasonicated GO (0.5 wt%)/diamond compound slurry, the average surface roughness Ra of wafer can reach 7.19 nm, which is 0.7% lower than 7.24 nm by pure diamond slurry. Experimental results demonstrate that the optimized planarization of sapphire wafer with high MRR and low surface roughness can be achieved using the GO compound slurry when the mechanical removal effect and the chemical reaction mechanism are in synergistic equilibrium. The XPS and EDS analyses clearly support the material removal model that a reactant aluminum carbonate layer and a residual carbon layer exist and both are efficiently removed by diamond abrasives. Results of this study can be applied to further explore high volume production of CMP of sapphire wafers.