Grinding and lapping induced surface integrity of silicon wafers and its effect on chemical mechanical polishing

Abstract

Grinding and lapping are two widely used machining processes for silicon wafer planarization. Their resultant surface integrity has a significant impact on subsequent polishing and hence the overall manufacturing cost. In this work, the morphologies and damage patterns of the ground and lapped silicon surfaces were comparatively investigated and the effect of surface integrity on subsequent chemical mechanical polishing (CMP) was understood. In the regime of ductile removal, the ground silicon surface had regularly distributed striations, but the lapped surface consisted of randomly and homogeneously distributed scratches. The lapped surface had a softer damage layer than the ground one because more stacking faults were induced in the silicon sublayer. In the subsequent process of CMP, the roughness of the lapped surface was decreased faster, but its corresponding material removal rate (MRR) was lower, in comparison to the CMP of the ground surface with the same starting roughness value. A bearing area ratio model was developed to elucidate the removal mechanism involved in polishing. The lapped surface was found to have a higher bearing area ratio than the ground, indicating that a larger surface area was removed, thus leading to a lower MRR.