Planarization Of Wafers Research Articles

Wafer-scale integration of GaAs optoelectronic devices with standard Si integrated circuits using a low-temperature bonding procedure

A methodology for the heterogeneous integration of epitaxial GaAs wafers with fully processed standard bipolar complementary metal-oxide-semiconductor Si wafers is presented. The complete low-temperature wafer bonding process flow, including procedures for the Si wafer planarization and GaAs substrate removal, has been developed and evaluated. The implementation of an in-plane optical link, consisting of an edge-emitting laser diode, a waveguide and a photodiode, is demonstrated.

Pad conditioning in chemical mechanical polishing

As circuits become increasingly complex and device sizes shrink, the demands placed on manufacturing processes increases. For successful manufacture of such circuits, high levels of wafer planarity are required. Chemical mechanical polishing (CMP) is a manufacturing process used to achieve global planarity. Studies have shown that the degree of planarity achieved is influenced by the pad properties. During polishing, the properties of the pad can deteriorate causing reduced polish rates and reduced planarity. It has been shown that this is caused by plastic deformation of the pad material, leading to glazed areas on the surface. Conditioning is used to regenerate the pad surface by breaking up these areas, but in doing so induces pad wear. As some areas of the pad will experience a higher degree of glazing, varying conditioning densities are necessary to counter this effect. The conditioning profile dictates the travel of the conditioning arm over the pad and hence the conditioning density experienced at each point. The aim of such a profile is to aid planarity by creating a uniform and constant removal rate over the whole wafer. The variations in pad properties between new and worn-out pads and the effect of conditioning in changing the pad properties will be examined. By examining correlations between conditioning densities experienced and pad properties over the radius of the pad, it is hoped to further understand the effect of conditioning on the process. Such understanding is vital in improving process reliability and yields in semiconductor manufacture.

Modeling and Experimental Analysis of the Material Removal Rate in the Chemical Mechanical Planarization of Dielectric Films and Bare Silicon Wafers

An analytic model of the material removal rate is proposed for chemical mechanical planarization (CMP). The effects of the applied pressure and the polishing velocity between the wafer surface and the pad surface are derived considering the chemical reaction as well as the mechanical bear-and-shear process. The mechanism of microscopic material removal is presented. The material removal rate is found less linearly correlated to the pressure and relative velocity between the pad and the wafer, which was predicted by the frequently cited empirical Preston equation obtained from glass polishing. [I. F. W. Preston, J. Soc. Glass. Technol., 11, 214 (1927)]. It provides the analytical modification of the Preston equation in the dielectrics CMP. The experimental results of authors and independent researchers are discussed. © 2001 The Electrochemical Society. All rights reserved.

Quality improvement of chemical-mechanical wafer planarization process in semiconductor manufacturing using a combined generalized linear modelling - non-linear programming approach

This paper is aimed at how to develop and utilize a specialized response surface method, combined with state-of-the-art mathematical programming techniques, for quality improvements of the chemical-mechanical planarization (CMP) process in semiconductor manufacturing. CMP is one of the fastest growing technologies that enables to polish the topography of interlayer dielectrics (ILDs) and to obtain a high degree of global planarity due to increasingly stringent requirements of photolithography between process steps. A wafer held on a carrier is rotated against a polishing pad in the presence of a silica-based alkaline slurry while applying a down-force onto it. Two major challenging works posed by CMP involve maintaining stable removal rate with polishing time and achieving acceptable within-wafer non-uniformity (WIWNU) over an entire die. In this research, to robustly characterize and therefore optimize such a still unclear and fully complex process, the response surface methodology (RSM) as an external modelling technique and non-linear programming (NLP) approaches as an optimum-seeking procedure are proposed to the bicriteria situation. An example with real CMP data is rigorously investigated, revealing that not only does the proposed method flexibly and appropriately portray CMP, but also helps locate the optimal parameter settings that attain better polishing quality.

Novel Alignment Method for Planarized Substrates in Electron Beam Lithography

We have developed an alignment mark structure for planarized substrates, that enables high alignment accuracy in electron beam lithography. Not only heavy metals but also light elements are used as marks. For multilevel metalization processes, we confirmed the advantages of buried heavy-metal marks by detection-signal simulation and exposure experiments. This mark structure allows the detection of alignment marks using an electron beam, even when they are covered by a SiO2 film up to a few micrometers thick or with metal films that prevent detection by an optical method. Buried light-element alignment marks, such as a SiO2 mark in a Si substrate, are also effective. Such marks are suitable for use prior to the gate-fabrication process, especially for the shallow groove isolation (SGI) process, because they do not cause heavy-metal contamination. Marks consisting of periodic narrow lines made with light elements are particularly suitable for wafer planarization processes.

The Effect of Pad Wear on the Chemical Mechanical Polishing of Silicon Wafers

The Chemical Mechanical Polishing process planarises wafers with a high degree of success, however wear on the polishing pad causes the planarisation rate and the post-process planarity to deteriorate. To date, there has been no method of predicting the effect of this wear on the wafer planarity. Using finite element models of the process for new and worn pads the wafer stress distribution on the wafer surface can be predicted. Equating high stresses to high material removal rates these models predict that the process should become ‘centre slow’ as the pad wears. This correlates well with experimental data.

Wear phenomena in chemical mechanical polishing

Chemical mechanical polishing (CMP) has become a primary method for planarization of semiconductor wafers. The CMP process is a tribochemical process, which involves a simultaneous interaction between a polishing slurry, a semiconductor wafer, and a polishing pad. Mechanical and chemical-assisted wear dominate the entire CMP process. The material, chemical, mechanical and lubricating properties of the three mentioned bodies determine the controllability and quality of CMP. For semiconductor wafers, the material removal rate, surface roughness, the number of defects, and the surface flatness are the benchmarks of CMP performance. In this work, we examined the polished surfaces of waters and pads, using an optical microscope, scanning electron microscope, atomic force microscope, and other surface analysis techniques. We investigated the properties vs. performance relationships of polishing pads, s;urries and wafers. We found that plastic deformation predominates the wear mechanisms of both wafer and pad materials. Wear of materials in CMP takes place over a wide range from the nanometer to micrometer scale.

Planar laterally oxidized vertical-cavity lasers for low-threshold high-density top-surface-emitting arrays

We introduce a novel device architecture that enables the fabrication of low threshold high density vertical-cavity surface-emitting laser (VCSEL) arrays. Our structure relies on a group of small via holes to access a buried AlGaAs layer for lateral oxidation. In contrast to the conventional method of exposing mesa sidewalls through etched pillars, this technique provides our VCSEL's with the benefits of oxide confinement without sacrificing wafer planarity. Maintaining wafer planarity is essential for the easy fabrication and contacting of densely packed devices. The devices operate at 827 nm, with a minimum threshold current of 200 μA, and a maximum output power of 3.15 mW.

半導体ウエハの化学機械研磨工程における光学式終点検出法

A novel end-point detection technique is proposed for planarization of semiconductor wafers by chemical mechanical polishing. In this technique, a local thickness variation of polished layer is observed in-situ in detail, instead of observing a mean thickness value of the whole layer with conventional technique. The detection head owns two sensors, and mounted on a rotating platen for polishing. The first sensor is a fluid gap gage for measuring a surface position of the polished layer. The second one is an optical pick-up for measuring a bottom position of the layer. A residual thickness value of the polished layer, which is a target of this end-point detection, can be known as difference of the both values. A prototype detector was constructed. The experimental results show a 0.1μm sensitivity and a capability for manufacturing use.

Chemical‐mechanical polishing of n—PbTe and n—Pb1‐xSnxTe crystals

AbstractPbTe and Pb1‐xSnxTe crystals are of very low hardness. Their mechanical treatment (cutting, lapping, polishing) results in the formation of a thick damaged surface layer (ENGEL et al.). The removing of the damaged layer by etch polishing affects the wafer planarity. The latter is of major importance when the wafers are used as substrates for epitaxial growth. The quality of the treated surfaces is significantly better when chemical‐mechanical polishing (CMP) is applied. For CMP of p‐PbTe and p‐Pb1‐xSnxTe BREITSAMETER et al. have proposed a solution containing potassium hexacyanoferrate (III), sodium hydroxide, glycerol or ethylenglycol. For CMP of Pb1‐xSnxTe STERNBERG and YELLIN have applied a solution of Br2 in HBr. This etchant, however, is strongly corrosive and requires the use of a special equipment.In the present work the conditions for CMP of n‐PbTe and n‐Pb1‐xSnxTe (x ∼ 0.2) with the etchant proposed by BREITSAMETER et al. have been investigated.

Metal polishing developments : D. J. Fishlock. Mechanical World and Engineering Record, v. 138, Mar. 1958, p. 102–106; Apr. 1958, p. 180–184

Chemical mechanical polishing (CMP) has become a primary method for planarization of semiconductor wafers. The CMP process is a tribochemical process, which involves a simultaneous interaction between a polishing slurry, a semiconductor wafer, and a polishing pad. Mechanical and chemical-assisted wear dominate the entire CMP process. The material, chemical, mechanical and lubricating properties of the three mentioned bodies determine the controllability and quality of CMP. For semiconductor wafers, the material removal rate, surface roughness, the number of defects, and the surface flatness are the benchmarks of CMP performance. In this work, we examined the polished surfaces of waters and pads, using an optical microscope, scanning electron microscope, atomic force microscope, and other surface analysis techniques. We investigated the properties vs. performance relationships of polishing pads, s;urries and wafers. We found that plastic deformation predominates the wear mechanisms of both wafer and pad materials. Wear of materials in CMP takes place over a wide range from the nanometer to micrometer scale.