Pipelined Analog-to-digital Converter Research Articles

A 10-Bit 40-MS/s Pipelined ADC With a Wide Range Operating Temperature for WAVE Applications

A 10-bit 40-MS/s analog-to-digital converter (ADC) that is suitable for wireless access in vehicular environment applications is introduced. In order to satisfy the severe requirement of a wide range operating temperature under the given constraints, the ADC was simplified by eliminating nonessential building blocks such as reference drivers, a sample-and-hold amplifier (SHA), and level shifters. The proposed internal signal amplification method extends the effective signal range in both multiplying digital-to-analog converter and flash ADC, as well as the error correction range. A new clock generation circuit for a SHA-less pipelined ADC removes the need for a higher frequency external clock. The prototype ADC was fabricated in a 180-nm CMOS process. The ADC core consumes 23.4 mW at 3.3-V/1.8-V supplies. The measured worst differential nonlinearity and integral nonlinearity were -0.52/+0.7 LSB and -0.86/ +0.9 LSB, respectively, at a temperature of -40 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> C. The signal-to-noise-and-distortion ratio stayed above 55 dB in the Nyquist condition in a temperature range of -40 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> C-125 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> C, which is about a 0.5 effective-number-of-bits drop from the room-temperature result.

A Domain Extension Algorithm for Digital Error Correction of Pipeline ADCs

A domain extension algorithm to correct the comparator offsets of pipeline analog-to-digital converters (ADCs) is presented, in which the 1.5-bit/stage ADC quantify domain is extended from a three-domain to a five-domain. This algorithm is designed for high speed and low comparator accuracy application. The comparator offset correction ability is improved. This new approach also promises significant improvements to the spurious-free dynamic range (SFDR), the total harmonic distortion (THD), the signal-to-noise ratio (SNR) and the minor analog and digital circuit modifications. Behavioral simulation results are presented to demonstrate the effectiveness of the algorithm, in which all absolute values of comparator offsets are set to |3Vref/8|. SFDR, THD and SNR are improved, from 34.62-dB, 34.63-dB and 30.33-dB to 60.23-dB, 61.14-dB and 59.35-dB, respectively, for a 10-bit pipeline ADC.

流水线模数转换器中的宽带电流型运算放大器

A novel bandwidth current operational amplifier was presented to meet the demand of video signal processing for a pipelined Analog-to-Digital Converter(ADC)with large dynamic ranges and higher operation speeds.In the system,the main amplifier adopts a cascode structure and the auxiliary amplifier is a current mode amplifier.In order to improve circuit speeds and to decrease parasitic capacitance,the input signal was applied to the source terminal.A current-mode feedback circuit was utilized to stabilize the out common mode voltage through adjusting the currents of the main amplifier and the amplifier was implemented in TSMC 0.18μm CMOS process with a consumer of 9.3mW.Experiment results show that the circuit has an open loop gain of 83.19 dB,a unity gain bandwidth of1.6GHz and a phase margin of 61.6°.A pipelined ADC for high-resolution video signal process using this current amplifier achieves a resolution of 10 bit and a sampling rate of 170MS/s.Compared with traditional amplifiers,the proposed amplifier shows a lower power dissipation and higher response speeds and satisfies the requirements of the video signal processing.

A pseudo-differential MDAC with a gain-boosting inverter for pipelined ADCs

In this paper, a power-efficient pseudo-differential (PD) multiplying digital-to-analog converter (MDAC) is presented for pipelined analog-to-digital converters (ADCs). The proposed MDAC eliminates the explicit common-mode feedback circuit which is required in fully-differential configurations without any power penalty. Furthermore, a new class-AB gain-boosting inverter is proposed to be used in PD MDAC structures for further power saving. This inverter provides dynamic load current with no significant static power consumption and achieves high DC gain using a new gain-boosting technique. To demonstrate the effectiveness of the proposed circuits, they are utilized in the realization of a 1.5-bit/stage 10 bit 100 MS/s pipelined ADC.

Foreground calibration technique of a pipeline ADC using capacitor ratio of Multiplying Digital-to-Analog Converter (MDAC)

A foreground calibration technique of a pipeline analog-to-digital converter (ADC) has been presented in this paper. This work puts an emphasis on erroneous ADC output occurring due to device mismatch, which, in any standard CMOS process boils down to capacitor mismatch. Deviation of gain of a multiplying digital-to-analog converter (MDAC), also known as the radix of a pipeline ADC stage, from its ideal values adds to the non-linearity of the ADC output. Capacitor mismatch is a major contributor for such an error. The proposed foreground calibration technique makes use of a simple arithmetic unit to extract the radix value from the ADC output for calibration. It uses a sinusoidal signal at the input for calibration purposes. The input sinusoidal signal can be sampled by the ADC clock at any rate for the calibration algorithm to be successful. Behavioral simulation of a pipeline ADC with 5% capacitor mismatch supports the established technique. To verify the calibration algorithm further, pipeline ADCs of different resolutions have been designed and simulated in a 0.18μm CMOS process.

FFT‐based calibration method for 1.5 bit/stage pipelined ADCs

SummaryA fast Fourier transform (FFT)‐based digital calibration method for 1.5 bit/stage pipeline analog‐to‐digital converter (ADC) is proposed in this paper. Capacitor mismatch and finite gain of the operational amplifier (OPAMP) can be overcome by the proposed calibration method. Given that the capacitor mismatch and the finite OPAMP gain cause the radix of all the stages of 1.5 bit/stage pipeline ADC to become unequal to 2, the FFT processor can be adopted to evaluate the actual radixes of all the stages and then generate new digital output to compensate for error caused by these non‐ideal effects. Moreover, as capacitor mismatch and the finite gain of OPAMP can be compensated, low‐gain OPAMP can be used in high‐performance ADC to reduce power dissipation; a small capacitor can then be adopted to save on space. An example of a 10 bit 1.5 bit/stage pipelined ADC with only an 8 bit circuit performance is implemented in 0.18 µm TSMC CMOS process. Circuit measurement result reveals that the signal‐to‐noise‐and‐distortion ratio of 51.03 dB with 11 dB improvement after calibration can be achieved at the sample rate of 1 MHz. Copyright © 2013 John Wiley &amp; Sons, Ltd.

A 1.2 V dual-channel 10 bit pipeline ADC in 55 nm CMOS for WLAN receivers

A power-efficient technique for pipeline analog-to-digital converters (ADCs) is proposed. By sharing amplifiers between I/Q channels, the power dissipation of the ADCs is reduced by almost one-half compared to conventional topologies, which makes this technique suitable for low-power direct-conversion WLAN receivers. A dual-channel ADC test chip is fabricated in 55 nm CMOS technology. The 10 bit ADC with on-chip reference generators dissipates 19.2 mW per channel from a 1.2 V supply. At an 80 MS/s sample rate, the measured spurious-free dynamic range, signal-to-noise and distortion ratio, and corresponding effective number of bits are 69.5 dB, 56.8 dB and 9.14 bits with a 1 MHz input frequency (fin), and 61.3 dB, 56.5 dB and 9.09 bits with a 15 MHz fin, respectively. The active area is 1.01 × 0.77 mm2.

A low power time-interleaved 10-bit 250-MSPS charge domain pipelined ADC for IF sampling

A 10-bit 250-MSPS two-channel time-interleaved charge-domain (CD) pipelined analog-to-digital converter (ADC) is presented. MOS bucket-brigade device (BBD) based CD pipelined architecture is used to achieve low power consumption. An all digital low power DLL is used to alleviate the timing mismatches and to reduce the aperture jitter. A new bootstrapped MOS switch is designed in the sample and hold circuit to enhance the IF sampling capability. The ADC achieves a spurious free dynamic range (SFDR) of 67.1 dB, signal-to-noise ratio (SNDR) of 55.1 dB for a 10.1 MHz input, and SFDR of 61.6 dB, SNDR of 52.6 dB for a 355 MHz input at full sampling rate. Differential nonlinearity (DNL) is +0.5/−0.4 LSB and integral nonlinearity (INL) is +0.8/−0.75 LSB. Fabricated in a 0.18-μm 1P6M CMOS process, the prototype 10-bit pipelined ADC occupies 1.8 × 1.3 mm2 of active die area, and consumes only 68 mW at 1.8 V supply.

Digital background calibration of capacitor mismatches and harmonic distortion in pipelined ADC

A correlation-based digital background calibration algorithm for pipelined Analog-to-Digital Converters (ADCs) is presented in this paper. The merit of the calibration algorithm is that the main errors information, which include the capacitor mismatches and residue amplifier distortion, are extracted integrally. A modified 1st pipelined stage is adopted to solve the signal overflow caused by the Pseudo-random Noise (PN) sequences. Behavioral simulation results verify the effectiveness of the algorithm. It improves the Signal-to-Noise-plus-Distortion Ratio (SNDR) and Spurious-Free-Dynamic-Range (SFDR) of the pipelined ADC from 41.8 dB to 78.3 dB and 55.6 dB to 98.6 dB, respectively, which is comparable to the prior arts.

Simulink Behavioral Modeling of a 10- bit Pipelined ADC

The increasing architecture complexity of data converters makes it necessary to use behavioral models to simulate their electrical performance and to determine their relevant data features. For this purpose, a specific data converter simulation environment has been developed which allows designers to perform time-domain behavioral simulations of pipelined analog to digital converters (ADCs). All the necessary blocks of this specific simulation environment have been implemented using the popular Matlab simulink environment. The purpose of this paper is to present the behavioral models of these blocks taking into account most of the pipelined ADC non-idealities, such as sampling jitter, noise, and operational amplifier parameters (white noise, finite DC gain, finite bandwidth, slew rate, and saturation voltages). Simulations, using a 10-bit pipelined ADC as a design example, show that in addition to the limits analysis and the electrical features extraction, designers can determine the specifications of the basic blocks in order to meet the given data converter requirements.

Immediate Calibration of Operational Amplifier Gain Error in Pipelined ADCs Using Extended Correlated Double Sampling

This paper introduces extended correlated double sampling (ECDS) as a new gain-calibration technique in pipelined analog-to-digital converters (ADCs). The proposed calibration simultaneously improves the effective dc gain and increases the maximum output swing of the opamps with given overdrive voltages. Furthermore, ECDS is immediate, thus avoiding the long convergence time associated with many background calibration schemes. This characteristic makes it desirable for applications where the ADC is on only briefly, such as wireless sensor networks (WSNs). An 11-bit 40-MS/s prototype pipelined ADC has been fabricated in 0.25-μm CMOS to demonstrate the proposed calibration technique. The active die area is 3.8 mm2 , and the analog power dissipation is 85 mW from a 2.5-V supply. With a 72-kHz input frequency, ECDS improves signal-to-noise-and-distortion ratio from 40.1 to 63.4 dB and spurious-free dynamic range from 41.8 to 75.7 dB.

A 10-bit 25-MS/s 1.25-mW Pipelined ADC With a Semidigital Gm-Based Amplifier

A semidigital Gm-based amplifier is proposed for a low-power pipelined analog-to-digital converter (ADC). The amplifier performs a class-AB operation by smoothly changing between a comparator-like semidigital driver and a continuous-time high-gain amplifier according to the input voltage difference. A 10-bit pipelined ADC with 2.5-bit/stage architecture is implemented in a 0.13- <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\mu\hbox{m}$</tex></formula> CMOS. The ADC consumes 1.25 mW at a sampling rate of 25 MS/s and achieves a Nyquist-rate figure-of-merit of 139 and 232 fJ/c-s without and with power consumption from a resistor ladder, respectively.

CONTRIBUTION TO THE ANALYSIS AND MODELING OF THE NON-IDEAL EFFECTS OF PIPELINED ADCs USING MATLAB

The present work analyses the non-ideal effects of pipelined analog-to-digital converters (ADCs), also sometimes referred to as pipeline ADCs, including the non-ideal effects in operational amplifiers (op-amps or OAs), switches and sampling circuits. We study these nonlinear effects in pipelined ADCs built using CMOS technology and switched-capacitor (SC) techniques. The proposed improved model of a pipelined ADC includes most of the non-idealities which affect its performance. This model, simulated using MATLAB, can determine the basic blocks specifications that allow the designer to meet given data converter requirements.

Non-binary Pipeline Analog-to-Digital Converter Based on &lt;i&gt;β&lt;/i&gt;-Expansion

This paper proposes a pipeline analog-to-digital converter (ADC) with non-binary encoding technique based on β-expansion. By using multiply-by-β switched-capacitor (SC) multiplying digital-to-analog converter (MDAC) circuit, our proposed ADC is composed by radix-β (1 < β < 2) 1 bit pipeline stages instead of using the conventional radix-2 1.5 bit/1 bit pipeline stages to realize non-binary analog-to-digital conversion. Also with proposed β-value estimation algorithm, there is not any digital calibration technique is required in proposed pipeline ADC. The redundancy of non-binary ADC tolerates not only the non-ideality of comparator, but also the mismatch of capacitances and the gain error of operational amplifier (op-amp) in MDAC. As a result, the power hungry high gain and wide bandwidth op-amps are not necessary for high resolution ADC, so that the reliability-enhanced pipeline ADC with simple amplifiers can operate faster and with lower power. We analyse the β-expansion of AD conversion and modify the β-encoding technique for pipeline ADC. In our knowledge, this is the first proposal architecture for non-binary pipeline ADC. The reliability of the proposed ADC architecture and β-encoding technique are verified by MATLAB simulations. key words: non-binary AD conversion, β-expansion, pipeline ADC, switched-capacitor circuits, multiply-by-β MDAC

Static Integral Nonlinearity Modeling and Calibration of Measured and Synthetic Pipeline Analog-to-Digital Converters

The integral nonlinearity (INL) modeling of pipeline analog-to-digital converters (ADCs) is investigated in this paper. The INL is divided into two distinct entities: a low code frequency (LCF) component and a high code frequency (HCF) component. Two static models are developed to represent the INL data. In both models, the LCF component is represented by a low-order polynomial. The HCF modeling is performed using two different basis functions: sinc and Gaussian. The structure of both HCF models is motivated by the pipeline architecture of the ADC under investigation. The model coefficients are estimated by applying the least-squares method to the measured INL data from two samples of a commercial pipeline ADC. The estimated HCF models are compared to each other and to previous models presented in the existing literature. In addition, the modeling methods are applied to synthetic HCF data generated by a pipeline ADC simulation model constructed in MATLAB. The INL models are then used to calibrate the synthetic ADCs, and the improvements in spurious free dynamic range are compared to those obtained when the ADCs are compensated by the INL data. Furthermore, the capability of the HCF modeling to calibrate a given ADC is tested by using the HCF model to compensate a synthetically generated ADC output in which only the measured HCF sequence and noise are added to the quantization process. The results show that the developed HCF models can achieve virtually complete calibration of the considered ADC.

A 12-bit Interpolated Pipeline ADC Using Body Voltage Controlled Amplifier

This paper presents a 12-bit interpolated pipeline analog to digital converter (ADC) using body voltage controlled amplifier for current biasing and common mode feedback loop (CMFB). The proposed body voltage control method allows the amplifier to achieve small power consumption and large output swing. The proposed amplifier has a power consumption lower than 15.6 mW, almost half of the folded cascode (FC) amplifier satisfying 12-bit, 400 MS/s ADC operation. Moreover, the proposed amplifier secures 600 mV output swing, which is 1-VDS wider compared with the telescopic amplifier. The 12-bit interpolated pipeline ADC using proposed amplifier is demonstrated by 1P9M 90 nm process with 1.2 V supply voltage. The ADC achieves ENOB of about 10-bit at 300 MS/s and an FoM of 0.2 pJ/conv. when the frequency of the input signal is sufficiently low.

A digital background calibration algorithm of a pipeline ADC based on output code calculation

This paper proposes a digital background calibration algorithm to correct linearity errors in a pipelined analog-to-digital converter (ADC). The algorithm does not modify the analog circuit of pipelined stages and calibrates the raw conversion output by using a backend digital logic. Based on the analysis of the output codes, the calibration logic estimates the bit weight of each stage and corrects the outputs. An experimental 14-bit pipelined ADC is fabricated to verify the algorithm. The results show that INL errors drop from 20 LSB to 1.7 LSB, DNL errors drop from 2 LSB to 0.4 LSB, SNDR grows from 57 to 65.7 dB and THD drops from −58 to −81 dB. The linearity of the pipelined ADC is improved significantly.

Successive approximation pipelined ADC with one clock cycle conversion rate

An N -bit successive approximation pipelined (SAP) analogue-to-digital converter (ADC) with a conversion rate equal to the clock frequency is presented. The ADC implements the successive approximation algorithm using parallelism and pipelining to sample the input and generate an N -bit digital output at each clock cycle. The latency is N clock cycles. The requirement for the residue circuit (high frequency analogue subtract and multiply) between pipeline stages in traditional pipelined ADCs is eliminated, which significantly reduces the sensitivity to comparator offset and component mismatch. The combination of energy efficient SAR sub-circuits with conversion rate greater than 1.0 GHz when implemented in CMOS nanotechnology makes the SAP ADC an attractive option for high performance wireless and wireline applications.

A Pipelined ADC With Metastability Error Rate &lt;formula formulatype="inline"&gt;&lt;tex Notation="TeX"&gt;$&amp;lt;$&lt;/tex&gt;&lt;/formula&gt;10&lt;formula formulatype="inline"&gt; &lt;tex Notation="TeX"&gt;$^{-15}$&lt;/tex&gt;&lt;/formula&gt; Errors/Sample

A prototype 10-bit 80-MS/s pipelined analog-to-digital converter (ADC) implemented in a 0.25-μm CMOS process is described. The prototype uses a combination of time-interleaved and lookahead operations to allow one clock period for comparator regeneration, reducing the bit error rate (BER) due to comparator metastability by a factor between 104 and 106. Also, the front-end sample-and-hold amplifier (SHA) previously used to provide a 1/2 clock period of regeneration time for the first-stage comparators in a lookahead pipelined ADC is eliminated [1], [2], reducing the power consumption and the input-referred noise. The analog power dissipation is 72 mW from a 2.5-V supply. At a sampling rate of 80 MS/s, the prototype achieves a peak signal-to-noise-and-distortion ratio of 58.3 dB for an input frequency of 80 kHz. Also, for a comparator bias current of 100 μA, extrapolations from measurements show that the BER is <;10-15 errors/sample.

A fast foreground digital calibration technique for pipelined ADC

Digital calibration techniques are widely developed to cancel the non-idealities of the pipelined Analog-to-Digital Converters (ADCs). This letter presents a fast foreground digital calibration technique based on the analysis of error sources which influence the resolution of pipelined ADCs. This method estimates the gain error of the ADC prototype quickly and calibrates the ADC simultaneously in the operation time. Finally, a 10 bit, 100 Ms/s pipelined ADC is implemented and calibrated. The simulation results show that the digital calibration technique has its efficiency with fewer operation cycles.