Successive approximation pipelined ADC with one clock cycle conversion rate

Abstract

An N -bit successive approximation pipelined (SAP) analogue-to-digital converter (ADC) with a conversion rate equal to the clock frequency is presented. The ADC implements the successive approximation algorithm using parallelism and pipelining to sample the input and generate an N -bit digital output at each clock cycle. The latency is N clock cycles. The requirement for the residue circuit (high frequency analogue subtract and multiply) between pipeline stages in traditional pipelined ADCs is eliminated, which significantly reduces the sensitivity to comparator offset and component mismatch. The combination of energy efficient SAR sub-circuits with conversion rate greater than 1.0 GHz when implemented in CMOS nanotechnology makes the SAP ADC an attractive option for high performance wireless and wireline applications.