Implementation of a high-speed flash ADC for high-performance pipeline ADCs in an 180nm CMOS process

Abstract

Pipeline Analog to Digital Converters (ADC) use a sub-ADC in each pipeline stage. They require a much higher sampling rate and less accuracy. For that reason Flash ADCs are predestined for sub-ADCs. In this paper a differential Flash ADC is presented for a targeted pipeline ADC with 16 Bit, 200 MS/s and a 1.5 Bit resolution per stage. The overall accuracy of the Flash ADC is 30mV and a typical propagation delay of around 400 ps is achieved. This corresponds to a sampling rate of 2.5 GS/s. In addition, a new numerical method for an effective simulation of the propagation delay and offset is presented.