Pipelined Analog-to-digital Converter Research Articles

A new pipelined analog-to-digital converter using current conveyors

A new pipelined analog-to-digital converter (ADC) using second-generation current conveyor (CCII) is presented. Two main building blocks of the pipelined ADC, sample-and-hold (S/H) circuit and multiplying digital-to-analog converter (MDAC) are constructed of CCII instead of operational amplifier (OA). Experimental results show that the proposed CCII-based pipelined ADC can work at 12.5 MHz with a 7.3-bit resolution. The DNL is within ?0.4 LSB and 0.4 LSB and INL is within ?0.8 LSB and 0.8 LSB, respectively. The pipelined ADC is realized in TSMC 0.35 ?m CMOS technology and consumes 29 mW under a 3.3 V power supply. The core size is 0.85×0.85 mm2.

Measuring Volterra Kernels of Analog-to-Digital Converters Using a Stepped Three-Tone Scan

The Volterra theory can be used to mathematically model nonlinear dynamic components such as analog-to-digital converters (ADCs). This paper describes how frequency-domain Volterra kernels of an ADC are determined from measurements. The elements of the Volterra theory are given, and practical issues are considered, such as methods for signal conditioning and finding the appropriate test signals scenario and suitable sampling frequency. The results show that, for the used pipeline ADC, the frequency dependence is significantly stronger for second-order difference products than for sum products and the linear frequency dependence was not as pronounced as that of the second-order Volterra kernel. It is suggested that the Volterra kernels have the symmetry properties of a specific box model, namely, the parallel Hammerstein system.

An Ultra-Energy-Efficient Wide-Bandwidth Video Pipeline ADC Using Optimized Architectural Partitioning

The classical pipeline analog-to-digital converter (ADC) architecture is analyzed to determine optimal partitioning for high effective resolution bandwidth (ERBW) and low-power consumption at reduced supply voltages. It is found that multibit inter-stage partitioning, in particular 2.5 bits per stage, is optimum for the reduction of power consumption in subsampling video ADCs for mobile/handheld receivers. To validate the analysis, a 1.5-V, 10-bit pipeline ADC for the digital video broadcast-handheld application was realized in a standard 3.3-V, 0.35-mum CMOS technology, with 2.5-2.5-2.5-4 partitioning employed. At the target sampling rate of 20.48 MS/s, measured results show that the converter achieves 56-dB SNR, 60-dB spurious-free dynamic range, 100-MHz ERBW and a power consumption of 19.5 mW. Energy consumption per conversion is only 0.19 pJ, making it the most energy-efficient 10-bit video-rate pipeline ADC reported to date

Gain Calibration Technique for Increased Resolution in FRC Data Converters

A feedforward residue compensation (FRC) data converter combines the benefits of a Nyquist rate analog-to-digital converter (ADC) with an oversampled converter. In this brief, the authors introduce a digital calibration technique that allows the FRC architecture to provide high resolution at high input signal frequencies. A high-performance pipeline ADC is used as an auxiliary converter to measure the quantization effects of an oversampled primary converter in the FRC architecture. A practical ADC architecture using a digital gain error calibration technique produces a 15-bit 70-Msample/s converter with greater than 100-dB spurious-free dynamic range. Simulation results are used to validate the architecture and gain calibration technique

Platform-based mixed signal design: Optimizing a high-performance pipelined ADC

We apply Platform-Based Design (PBD) to the power optimization of a 14 bit, 80 MS/s pipelined Analog-to-Digital Converter (ADC) in a mixed signal formulation. A platform is a library of components and interconnects, each characterized with a set of behavioral, performance and composition models, that is used to raise the level of abstraction to enable system-level design. PBD is a meet-in-the-middle methodology that consists of two phases. The bottom-up phase generates a set of platform libraries that are exploited in the system hierarchy. The top-down phase allows exploring feasible solutions within the platform libraries and selecting the optimum implementation. To evaluate the cost of each implementation, the behavioral models available through platform abstraction are used both for digital and analog components. We provide an example of the use of the methodology and its features for analog circuits by modeling two amplifiers with different topologies as analog components, showing details of the analog characterization process. Then, we create a mixed signal platform library as a combination of an analog and a digital platform (bottom-up phase). The top-down phase performs optimization across the analog/digital boundary to minimize power consumption constrained to given noise and linearity requirements. Simulation results show that interesting power saving can be achieved, as much as 64% compared with an original hand-optimized ADC.

Digital Background Correction of Harmonic Distortion in Pipelined ADCs

Pipelined analog-to-digital converters (ADCs) are sensitive to distortion introduced by the residue amplifiers in their first few stages. Unfortunately, residue amplifier distortion tends to be inversely related to power consumption in practice, so the residue amplifiers usually are the dominant consumers of power in high-resolution pipelined ADCs. This paper presents a background calibration technique that digitally measures and cancels ADC error arising from distortion introduced by the residue amplifiers. It allows the use of higher distortion and, therefore, lower power residue amplifiers in high-accuracy pipelined ADCs, thereby significantly reducing overall power consumption relative to conventional pipelined ADCs

Digital Background Calibration of Capacitor-Mismatch Errors in Pipelined ADCs

A digital background calibration technique is proposed to correct for the linearity error due to capacitor mismatches in pipelined analog-to-digital converters (ADCs). During the normal ADC operation, it randomly swaps the feedback capacitor with the sampling capacitor(s) in the multiplying digital-to-analog converter (MDAC) of each pipeline stage in the pipelined ADC. The capacitor-mismatch errors in all pipeline stages are then concurrently measured and corrected in the digital domain. The proposed technique can be utilized in both single-bit and multibit MDACs. Owing to its simple iterative algorithm for capacitor-mismatch error calibration, its implementation requires minimal additional digital hardware. Behavioral simulation results show that, using the proposed calibration technique, the signal-to-noise-plus-distortion ratio is improved from 10 to 12.5bits and the spurious-free dynamic range is increased from 65 to 95 dB, in a 13-bit pipelined ADC with sigma=0.25% capacitor mismatches

Continuous Digital Calibration of Pipeline A/D Converters

This paper describes a novel continuous calibration technique for pipeline analog-to-digital converters (ADCs). The new scheme utilizes an existing digital calibration algorithm and extends it to work in real time. The goal is to digitally calibrate the pipeline ADCs in the background without interrupting the normal operation of the converter. The concept behind the digital calibration algorithm is described and simulated using a 1-bit/stage pipeline architecture. Dominant static error mechanisms present in pipeline architectures are identified and discussed. These errors are successfully corrected by the implemented digital calibration algorithm. The calibration scheme is transparent to the overall system performance and is demonstrated using a 14-bit ADC with a 1-bit/stage architecture and 16 identical stages. The first seven stages in the pipeline are calibrated. Continuous calibration is realized using a hardware description language and two extra stages located at the end of the pipeline. The extra stages are only used during the calibration process. Verilog implementations of a stage-and-error-correction logic, as well as a finite state machine to control the calibration process, are presented. The real-time digital calibration technique is verified and successfully demonstrated using the Verilog-XL simulator

55-mW 200-MSPS 10-bit Pipeline ADCs for Wireless Receivers

A new power reduction technique for analog-to-digital converters (ADCs) is proposed in this paper. The power reduction technique is a kind of amplifier sharing technique and it is suitable for ADCs in a wireless receiver. A test chip, which contains two ADCs, is fabricated in 90-nm 1-poly 7-metal CMOS technology. The 10-bit ADC dissipates 55 mW from 1.2-V supply, when the ADC operates at 200 mega-samples per second (MSPS). The 10-bit, 200-MSPS ADCs achieve maximum differential nonlinearity (DNL) of 0.66 least significant bit (LSB), maximum integral nonlinearity (INL) of 1.00 LSB, a spurious-free dynamic range (SFDR) of 66.5 dB and a peak signal-to-noise plus distortion ratio (SNDR) of 54.4 dB that corresponds to 8.7 effective number of bits (ENOB). The active area is 1.8 mm times 1.4 mm

A background calibration technique for multibit/stage pipelined and time-interleaved ADCs

A digital background calibration technique to compensate for the nonlinearity and gain error in the sub-digital-to-analog converter (SDAC), and the operational amplifier finite dc gain in multibit/stage pipelined analog-to-digital converter (ADC) is proposed. By injecting subtractive calibration voltages in a modified conventional multibit multiplying DAC and performing correlation based successive coefficient measurements, a background calibration is performed. This calibration technique does not need an accurate reference voltage or an increasing in the SDAC resolution. A global gain correction essential for time-interleaved ADCs is presented. Simulation results show that in the presence of realistic capacitor and resistance mismatch and finite op-amp gain, this technique improves the linearity by several bits in single and multi-channel pipelined ADC

A 12-bit 20-Msample/s pipelined analog-to-digital converter with nested digital background calibration

A 12-bit 20-Msample/s pipelined analog-to-digital converter (ADC) is calibrated in the background using an algorithmic ADC, which is itself calibrated in the foreground. The overall calibration architecture is nested. The calibration overcomes the circuit nonidealities caused by capacitor mismatch and finite operational amplifier (opamp) gain both in the pipelined ADC and the algorithmic ADC. With a 58-kHz sinusoidal input, test results show that the pipelined ADC achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 70.8 dB, a peak spurious-free dynamic range (SFDR) of 93.3 dB, a total harmonic distortion (THD) of -92.9 dB, and a peak integral nonlinearity (INL) of 0.47 least significant bit (LSB). The total power dissipation is 254 mW from 3.3 V. The active area is 7.5 mm/sup 2/ in 0.35-/spl mu/m CMOS.

Code-Width Testing-Based Compact ADC BIST Circuit

This paper proposes a new analog-to-digital converter (ADC) built-in self-test (BIST) scheme based on code-width and sample-difference testing that does not require a slope-calibrated ramp signal. The proposed BIST scheme can be implemented by a simple digital circuit whose gate count is only approximately 550. The proposed BIST scheme is verified by simulation with 138 test circuits of 6-b pipeline ADC with arbitrary faults. Simulation results show that it effectively detects not only the catastrophic faults but also some parametric faults. The simulated fault coverage is approximately 99%.

Low-power pipeline ADC for wireless LANs

In this paper, a 10-bit 40-MS/s analog-to-digital converter (ADC) is presented. A power consumption of 12 mW was achieved by using a time-interleaved and pipelined architecture with shared operational amplifiers. This circuit was fabricated in a 2.5-V 0.25-/spl mu/m technology with metal-oxide-metal capacitors. Experimental results are within design ranges and are in good agreement with simulation data. It turns out that the proposed Nyquist-rate ADC provides a potential solution for low-power high-speed applications, e.g., wireless LANs.

10-비트 200MS/s CMOS 병렬 파이프라인 아날로그/디지털 변환기의 설계

본 연구에서 매우 정밀한 샘플링을 필요로 하는 고해상도 비디오 응용면을 위하여 병렬 파이프라인 아날로그 디지털 변환기(ADC)를 설계하였다. 본 ADC의 구조는 4 채널의 10-비트 파이프라인 ADC를 병력 time-interleave로 구성한 구조로서 이 구조에서 채널 당 샘플링 속도의 4배인 200MS/s의 샘플링 속도를 얻을 수 있었다. 변환기에서 핵심이 되는 구성요소는 Sample and Hold 증폭기(SHA), 비교기와 연산증폭기이며 먼저 SHA를 전단에 설치하여 시스템 타이밍 요구를 완화시키고 고속변환과 고속 입력신호의 처리론 가능하게 하였다. ADC 내부 단들의 1-비트 DAC, 비교기 및 2-이득 증폭기는 한 개의 switched 캐패시터 회로로 통합하여 고속동작은 물론 저 전력소비가 가능한 특성을 갖도록 하였다. 본 연구의 연산증폭기는 2단 차동구조에 부저항소자를 사용하여 높은 DC 이득을 갖도록 보강하였다. 본 설계에서 각 단에 D-플립플롭(D-FF)을 사용한 지연회로를 구성하여 변환시 각 비트신호를 정렬시켜 타이밍 오차를 최소화하였다. 된 변환기는 3.3V 공급전압에서 280㎽의 전력소비를 갖고 DNL과 INL은 각각 +0.7/-0.6LSB, +0.9/-0.3LSB이다. This paper introduces the design or parallel Pipeline high-speed analog-to-digital converter(ADC) for the high-resolution video applications which require very precise sampling. The overall architecture of the ADC consists of 4-channel parallel time-interleaved 10-bit pipeline ADC structure a]lowing 200MSample/s sampling speed which corresponds to 4-times improvement in sampling speed per channel. Key building blocks are composed of the front-end sample-and-hold amplifier(SHA), the dynamic comparator and the 2-stage full differential operational amplifier. The 1-bit DAC, comparator and gain-2 amplifier are used internally in each stage and they were integrated into single switched capacitor architecture allowing high speed operation as well as low power consumption. In this work, the gain of operational amplifier was enhanced significantly using negative resistance element. In the ADC, a delay line Is designed for each stage using D-flip flops to align the bit signals and minimize the timing error in the conversion. The converter has the power dissipation of 280㎽ at 3.3V power supply. Measured performance includes DNL and INL of +0.7/-0.6LSB, +0.9/-0.3LSB.

A Practical Self-Calibration Scheme Implementation for Pipeline ADC

An efficient pipeline analog-to-digital converter (ADC) self-calibration implementation is presented. The technique uses a highly linear on-chip analog ramp generator, performs a simplified on-chip integral nonlinearity (INL) measurement, and extracts the compensation coefficients. Except for the ramp generator, the whole calibration is performed in the digital domain and is done at the nominal ADC speed (at-speed). The approach does not require any modification to the original analog section of the ADC. The INL measurement can be carried off-chip to simplify the production testing or to perform performance verification in the application environment. Simulation and measurement results show an INL improvement of more than 2 bits (from /spl plusmn/2.1 LSB to /spl plusmn/0.5 LSB).

Data Converter for Multistandard Mobile Phones

This paper describes an analog to digital converter (ADC) for mobile communication systems using a direct down conversion architecture. The ADC can be programmed to meet the requirements of different communication standards, including GSM (Global System for Mobile communication) and WCDMA (Wideband Code Division Multiple Access). The ADC is realized with a pipeline ADC architecture for WCDMA and a Sigma-Delta architecture for GSM. In order to have an optimized area and power consumption, the basic building blocks (opamps) of the converters are shared between the two converter architectures. The entire ADC consumes about 5.5 mW and occupies an active area of about 0.36 mm2. A test circuit has been developed and fabricated and measurements show that both the required programmability and the required performance can be obtained using the proposed configurations.

Capacitance Mismatch Evaluation for Low-power Pipeline ADC Design

It is known that the capacitance mismatch affects the nonlinearity of pipeline analog-to-digital converters (ADCs) and that larger capacitances tend to have a smaller mismatch. On the other hand, small capacitances are desirable because they reduce the current consumption. Therefore, to achieve a low-power, high-resolution ADC, it is necessary to perform capacitance mismatch evaluation and determine the appropriate capacitance.In this letter, a method for capacitance-mismatch measurement and the experimental results are described. The measurement results show that the mismatch is sufficiently small at the capacitance determined based on the noise requirement for 0.13-µm CMOS ADCs.

Least Mean Square Adaptive Digital Background Calibration of Pipelined Analog-to-Digital Converters

We present an adaptive digital technique to calibrate pipelined analog-to-digital converters (ADCs). Rather than achieving linearity by adjustment of analog component values, the new approach infers component errors from conversion results and applies digital postprocessing to correct those results. The scheme proposed here draws close analogy to the channel equalization problem commonly encountered in digital communications. We show that, with the help of a slow but accurate ADC, the proposed code-domain adaptive finite-impulse-response filter is sufficient to remove the effect of component errors including capacitor mismatch, finite op-amp gain, op-amp offset, and sampling-switch-induced offset, provided they are not signal-dependent. The algorithm is all digital, fully adaptive, data-driven, and operates in the background. Strong tradeoffs between accuracy and speed of pipelined ADCs are greatly relaxed in this approach with the aid of digital correction techniques. Analog precision problems are translated into the complexity of digital signal-processing circuits, allowing this approach to benefit from CMOS device scaling in contrast to most conventional correction techniques.

Background calibration techniques for multistage pipelined ADCs with digital redundancy

The proposed digital background calibration scheme, applicable to multistage (pipelined or algorithmic/cyclic) analog-to-digital converters (ADCs), corrects the linearity errors resulting from capacitor mismatches and finite opamp gain. A high-accuracy calibration is achieved by recalculating the digital output based on each stage's equivalent radix. The equivalent radices are extracted in the background by using a digital correlation method. The proposed calibration technique takes advantage of the digital redundancy architecture inherent to most pipelined ADCs. In the proposed method, the SNR is not degraded from the pseudorandom noise sequence injected into the system. A two-channel ADC architecture with negligible overhead is also proposed to significantly improve the efficiency of the digital correlation. Simulation results confirm that 16-bit linearity can be achieved after calibration for an ADC with /spl sigma/=0.1% capacitor mismatches and 60 dB opamp gain.

A 9-b 40-MSample/s reconfigurable pipeline analog-to-digital converter

In this paper, a reconfigurable pipeline analog-to-digital converter (ADC) architecture is proposed. Based on dynamic performance measurements, the best performance configuration will be chosen from a collection of possible configurations. A 40-MSample/s 9-b reconfigurable pipeline ADC is designed and implemented in Taiwan Semiconductor Manufacturing Corporation's (TSMC's) 0.25-/spl mu/m single-poly CMOS digital process. The chip is measured for all the configurations under different temperatures to prove the reconfiguration will provide significant effective number of bits (ENOB) improvement among the set of configurations. The active area of the design is 5.9 mm/sup 2/. The power consumption is 425 mW.