A 1.2 V dual-channel 10 bit pipeline ADC in 55 nm CMOS for WLAN receivers

Abstract

A power-efficient technique for pipeline analog-to-digital converters (ADCs) is proposed. By sharing amplifiers between I/Q channels, the power dissipation of the ADCs is reduced by almost one-half compared to conventional topologies, which makes this technique suitable for low-power direct-conversion WLAN receivers. A dual-channel ADC test chip is fabricated in 55 nm CMOS technology. The 10 bit ADC with on-chip reference generators dissipates 19.2 mW per channel from a 1.2 V supply. At an 80 MS/s sample rate, the measured spurious-free dynamic range, signal-to-noise and distortion ratio, and corresponding effective number of bits are 69.5 dB, 56.8 dB and 9.14 bits with a 1 MHz input frequency (fin), and 61.3 dB, 56.5 dB and 9.09 bits with a 15 MHz fin, respectively. The active area is 1.01 × 0.77 mm2.