Analysis and Modeling of Imperfections in Multi-Bit Per Stage Pipelined ADCs

Abstract

In this paper, an approach to estimate signal to noise ratio (SNR) and effective number of bits (ENOB) in nonideal multi-bit stages of pipelined analog to digital converters (ADCs) is presented. The most significant error sources in multistage ADCs are the capacitor mismatch and the finite and imprecise gain of amplifier. Output voltage of each stage in pipelined ADC is modeled by an ideal and a nonideal output, where nonideal output is the error due to circuit imperfections in each stage. Using an appropriate model, the SNR and ENOB due to circuit nonidealities and in terms of standard deviation of random errors are calculated. Simulation results show the accuracy of the analytical proposed approach in estimation of SNR and ENOB in multi-bit per stage pipelined converters.