Abstract

Problem statement: Pipelined architecture is considered to be the most suitable for high-speed and high-resolution applications among varies Nyquist Analogue to Digital Converters (ADCs) in nowadays digital signal processing domain. But the pipeline power consumption is growing with the technology scaling. For a pipeline ADC with high speed and high resolution, the fore-end track and hold amplifier and residual amplifier occupies the most power consumption of the whole system, so new and novel methods is needed to lower the amplifier power consumption. Approach: Different from the traditional use of close-loop amplifier, open-loop amplifier is used as the first-stage residual amplifier, which greatly decreases the system power consumption and design difficulty. To correct the nonlinear error introduced by the open-loop amplifier, backend digital correction is applied. To validate the rationality and correctness of the method and confirm the design parameters, Verilog-A is used to build a behavioural model, Cadence simulation tool Spectre is used to get the result. Results: From the simulation result of the behavioural model, we get the Differential Nonlinearity (DNL) of the digitally backend correction ADC is -0.25∼0.25, Integral Nonlinearity (INL) is -0.5∼0.25, Spurious Free Dynamic Range (SFDR) is 77.8dB. The Total Harmonic Distortion (THD) of the system after correction is calculated to be 73.66dB, so the Effective Number of Bits (ENOB) of the is 11.78 bits. Conclusion: Digitally assisted backend correction is a novel approach to lower the power consumption of pipeline ADCs, which makes great significance in mixed signal system design. The use of open-loop amplifier instead of traditional closed-loop amplifier can effectively decrease the design difficulty and design process than before. Only the first stage residual amplifier is changed to open-loop in this article and this substitution can also be replicated in the track and hold circuit and the succeeding stages.

Highlights

  • In deep submicron integrated circuit design and manufacture, digital signal processing develops fast, which makes higher speed and higher resolution Analogue to Digital Converters (ADCs) necessary

  • Signal processing and other applications that occupy the market, pipeline ADC continues to be the architecture of choice for high sample rate and high resolution analogue to digital converters

  • The trend in the market place is clearly presenting the needs of very high speed, high volume, low cost ADCs in both stand alone and integrated applications

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Summary

INTRODUCTION

In deep submicron integrated circuit design and manufacture, digital signal processing develops fast, which makes higher speed and higher resolution ADCs necessary. Verilog-A is a high- level language developed to establish the structure and behavior model for analog and mixed signal systems. It is considered an extension of the IEEE 1364 Verilog HDL specification for digital design. Open-loop amplifier is used in a 12- analogue and mixed signal circuit Behavioural bit 40MSPS digitally assisted backend correction modelling. Verilog-A is specified for the modelling of analogue circuit and in this hardware language, the properties and non-ideal elements can be precisely described, so the precision of the simulation can be greatly improved. The gain error of the open-loop amplifier, INL, DNL and SFDR of the ADC are simulated by Cadence Spectre

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