Pipelined Analog-to-digital Converter Research Articles

Rapid digital background calibration of bit weights in pipelined SAR ADC based on multi-PN injection

This brief presents a digital background calibration technique based on a dual-comparator architecture, aimed at addressing capacitor mismatch, residual gain error, and residue amplifier (RA) nonlinearity in pipelined successive-approximation-register (pipelined SAR) analog-to-digital converters (ADCs). Although numerous reports have documented bit weight calibration in pipelined SAR ADCs, none have been comprehensive, with op-amp nonlinearity never previously addressed. For the first time, we also consider and resolve the randomness issue of PN sequences following window sampling. Behavioral simulation results demonstrate the effectiveness of this technique, with the SNDR and SFDR performance of a 12-bit two-stage pipelined SAR ADC improving from 52.2 dB and 65.5 dB to an average of 68.8 dB and 91.0 dB, respectively. The convergence speed of this calibration algorithm is 0.6M samples, outpacing all previously published bit weight calibration works.

Digital background calibration algorithm for pipelined ADC based on time-delay neural network with genetic algorithm feature selection

This paper presents a novel background calibration method for pipelined analog-to-digital converters (ADCs) using a time-delay neural network (TDNN), which is optimized through genetic algorithm (GA) techniques. The proposed technique leverages TDNN to create enhanced feature sets, significantly improving the calibration of nonlinear errors exhibiting memory effects. It harnesses the GA's global optimization capabilities for feature selection, effectively reducing the feature dimension and consequently alleviating the NN's computational burden. A parallel pipeline architecture is devised for the calibration circuit, with its implementation realized on FPGA to facilitate forward inference processing. The inference circuit is synthesized using TSMC's 90 nm CMOS process, achieving a power consumption of 40.11 mW and an area of 0.45 mm2. Simulations based on MATLAB for a 14-bit Pipelined ADC demonstrate that the proposed calibration method significantly improves the SFDR from 59.77 dB to 165.52 dB, and ENOB from 8.79 bits to 19.23 bits, surpassing the target ADC's specifications. Moreover, the dimensionality of features is effectively reduced by up to 34 % without compromising the calibration performance.

A Calibration Scheme for a 800-Ms/s 14 Bit Pipelined ADC in 28-nm CMOS

Abstract A calibration scheme is proposed to compensate linear and nonlinear errors including offset, cap mismatch, second- and higher-order harmonics and memory induced errors in pipelined analog-to-digital converters (ADCs). The alternating minimization (AM) algorithm is proposed to accurately estimate the coefficients of the errors. As an accurate input value is hardly acquired in practical measurements, instead, the proposed scheme estimates the input and the error coefficients jointly. Once the error coefficient was calculated, it will be recorded in a lookup table (LUT). The scheme has been demonstrated in a 800-Ms/s 14-bit pipelined ADC fabricated in a 28nm CMOS process, which features a signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR) improvement of 2.49 dB and 11.49 dB at 800-Ms/s.

A 2nd-order noise-shaping SAR-assisted pipeline ADC with order-boosted gain-error-shaping

This paper presents a 4th-order interstage gain error shaping (GES) technique in pipeline successive approximation register (SAR) analog-to-digital converters (ADCs), which can substantially suppress the in-band quantization leakage error induced by the gain error. It is realized by simply arranging a low-order cascaded-integrator feed-forward (CIFF) structure in the first stage. In addition, the comparator noise and quantization error can be shaped together with the gain error in the proposed architecture. Verified by simulation in a 28-nm CMOS process, the prototype achieves a signal-to-noise-and-distortion ratio (SNDR) of 77.8 dB over 25-MHz bandwidth (BW) with oversampling ratio (OSR) of 8. Within a gain error range of −33 % to +33 %, the SNDR of the ADC deviates less than 3 dB. Under a 1 V supply voltage, the ADC consumes 3.75 mW and exhibits a Scherier figure of merit (FoMs) of 176 dB.

Genetic neural network based background calibration method for pipeline ADC

This article presents a pipeline analog-to-digital converter (ADC) background calibration method that combines genetic algorithm (GA) and neural network (NN) algorithm. The proposed method uses ADC outputs or individual stage sub-ADC outputs for NN training, employs GA for global optimization of the NN's initial setup to avoid local optima traps, and utilizes a parallel pipeline architecture to create a high-throughput calibration circuit with optimized multiply-accumulator (MAC) to minimize resource consumption. Through simulation on a 6-stage 14-bit pipelined ADC model, the proposed method demonstrated superiority over traditional calibration techniques and other NN-based calibration strategies. Specifically, after calibration, the signal-to-noise ratio (SNDR), spurious-free dynamic range (SFDR), and effective number of bits (ENOB) are significantly improved from 57.72 dB, 59.77 dB, and 8.79 bits to 104.61 dB, 152.64 dB, and 17.08 bits, respectively.

Multipurpose error calibration of pipeline analog‐to‐digital converters using decision points of the residue curve in sub‐analog‐to‐digital converters

SummaryA new mechanism of digital background calibration in pipeline analog‐to‐digital converters (ADCs) is expressed. The presented technique calibrates various errors like capacitor mismatch, finite DC gain of the amplifier, third‐order nonlinearity, and fifth‐order nonlinearity, so it is called multipurpose. In this method, the error coefficients are identified by estimation of the output code of the decision points in the voltage transfer characteristic (VTC) of the pipeline stages. To achieve sufficient decision points in the VTCs of the pipeline stages, one threshold level of one comparator of the sub‐ADC is shifted, and then the digital output is calibrated by capturing the error coefficients. The digital logic of this method is simple and does not require special analog circuits. The introduced calibration mechanism is evaluated for the first five stages of a 12‐bit 100 MS/s pipeline ADC. The required time for the calibration is 1.5 ms. By applying this method, the signal‐to‐noise and distortion ratio (SNDR) and spurious‐free dynamic range (SFDR) in order are enhanced from 46.44 and 50.53 dB to 69.92 and 74.04 dB, respectively.

A neural network‐based error correction in the first‐stage residue of pipelined analog to digital converters

SummaryAn analog background calibration approach is presented for the full calibration of pipeline analog‐to‐digital converters (ADCs). A well‐trained neural network acts close to the ideal 1.5‐bit stage, and its residue is compared with the real 1.5‐bit stage including gain error and amplifier nonlinearities. The detected error is used to compensate for the imperfect residue using four calibration polynomial coefficients. The corrected residue enters the second stage of the pipeline ADC and follows a normal path to achieve high resolution. The introduced structure is verified in a 12‐bit pipelined ADC composed of 11 stages; the first 10 stages have a 1.5‐bit structure, while the last stage is a 2‐bit flash. The sampling frequency is 100 MHz, and 10% non‐ideal factors (5% for each of the nonlinear and gain errors and 10% for the aggregated error) are considered for the first stage, while the input is 19.5 MHz sinusoidal waveform. A random noise is applied to the input to limit the effective number of bits (ENOB) to almost 11.8. The evaluation parameters of the ADC are extracted, signal‐to‐noise and distortion ratio increases from 39.14 to 72.91 dB, spurious free dynamic range improves from 40.94 to 79.69 dB, and the ENOB enhances from 6.2 to 11.82. The presented mechanism shows an acceptable accuracy in the high‐speed and high‐resolution ADCs.

Design and Analysis of 16-bit pipelined subranging SAR ADC and TDC

Analog to digital converters plays an important role in medical and signal processing applications. This paper proposes a 16-bit time based analog to digital converter (ADC) architecture by combining SAR Analog to Digital Converter and Vernier Time to Digital Converter. SAR analog to digital Converter is best suited for low power, high resolution and moderate applications. Vernier Time to Digital Converter with a high resolution to increase the conversion gain of VTC. The SAR ADC and Vernier TDC are pipelined to increase the conversion speed and reduce the area, power dissipation significantly smaller. A 16-bit combined pipelining SAR ADC and Vernier TDC was designed and simulated in Tanner EDA Tool.

A low power 16-bit 50 MS/s pipeline ADC with 104 dB SFDR in 0.18 μm CMOS

This paper presents a low-power 16-bit 50-MS/s pipeline analog-to-digital converter (ADC). An improved switched-capacitor bias technique is proposed to reduce power consumption while maintaining excellent performance, and a novel bootstrapped switch is implemented to improve the linearity further. An INL-(integral nonlinearity) based capacitor mismatch calibration is proposed to calibrate the capacitor match accuracy to the 16-bit level. The pipeline ADC is fabricated in a 0.18 μm mixed-signal CMOS process and the core size is 1.8 mm2. The implemented ADC is measured at a 50 MHz sampling rate under 1.8 V supply. After foreground calibration for capacitor mismatch errors, it achieves beyond 100 dB spur-free dynamic range (SFDR) and 75.3 dB signal-to-noise ratio (SNR). At the same time, the power consumption is 70.2 mW with 0.29 pJ/conv-step FOM (Figures-of-Merit).

A new ripple carry adder structure based on a swing‐boosted full adder for concurrent error correction in low‐resolution pipeline analog‐to‐digital converters

SummaryA ripple carry adder (RCA) structure is presented which can concurrently correct a gain error in low‐resolution pipeline analog‐to‐digital converters (ADCs). The RCA is composed of a new swing‐boosted full adder (FA) based on the transmission gate (TG) technique. So, it is low‐power, high‐speed, and full‐swing with high driving capability. In 90 nm technology, the results of power, delay, and power‐delay‐product (PDP) of the FA are 1.5296 μW, 2.1141 ns, and 3.2337 fJ, respectively. The RCA with an area of 408.09 μm2 is evaluated by a 3‐bit pipeline ADC with 1.5‐bit per stage. When the erroneous codes are passed through the RCA, the maximum and minimum integral nonlinearity (INL) are improved by 19.83% and 90.98%, while the maximum and minimum of the differential nonlinearity (DNL) are improved by 50%, and 42.06%, respectively.

A 12bit 1.6 GS/s pipelined ADC with multi-level dither injection achieving 68 dB SFDR over PVT

This paper presents a 12-bit 1.6 GS/s pipelined analog-to-digital converter (ADC) in a 40-nm CMOS process. A novel dual-capacitor dither injection technique was proposed, based on a randomize multi-level uniform logic, aimed at leveraging multi-level signal jitter to disperse higher-order harmonics and spurious signals within the spectrum. The technique proves highly effective in preserving the linearity of high-speed pipeline ADCs under Process, Voltage, and Temperature (PVT) variations. Additionally, a high-speed amplifier with SC net was designed, and its matching bias circuit design can achieve configurable performance adjustment according to circumstances. Measurement results show that the ADC attains an impressive Signal-to-Noise and Distortion Ratio (SNDR) of 55.9 dB and Spurious-Free Dynamic Range (SFDR) of 71.7 dB at the Nyquist frequency. Furthermore, the SFDR variation remains below 4.2 dB over the temperature range of −40 °C–85 °C.

A calibration-free 10.7 fJ/conv.-step 12-bit 120-MS/s pipelined SAR ADC in 40nm CMOS

A calibration-free 12-bit 120-MS/s 2-stage pipelined successive approximation register (pipelined SAR) analog-to-digital converter (ADC) is presented in this paper. In asynchronous SAR ADCs, capacitive digital-to-analog converters (CDACs) are designed with bottom-plate sampling to improve sampling accuracy and split-capacitor array to save switching energy. Furthermore, both reference scaling technique and a PVT-stabilized closed-loop residue amplifier are implemented in this design to obtain an accurate inter-stage gain, enabling no additional calibration required in the pipelined SAR ADC. The prototype ADC in 40nm CMOS technology achieves a peak signal-to-noise-distortion ratio (SNDR) of 73.4 dB and 88.91dB spurious-free-dynamic-range (SFDR) at 120 MS/s sampling rate, consuming 4.88 mW power from 0.9 V supply voltage, and corresponding to an excellent figure-of-merit (FoM) of 10.7 fJ/conv.-step.

A Multi-Dimensional Calibration Based on Genetic Algorithm in a 12-Bit 750 MS/s Pipelined ADC.

As the preferred architecture for high-speed and high-resolution analog-to-digital converters (ADC), the accuracy of pipelined ADC is limited mainly by various errors arising from multiple digital-to-analog converters (MDAC). This paper presents a multi-dimensional (M-D) MDAC calibration based on a genetic algorithm (GA) in a 12-bit 750 MS/s pipelined ADC. The proposed M-D MDAC compensation model enables capacitor mismatch and static interstage gain error (IGE) compensation on the chip and prepares for subsequent background calibration based on a pseudo-random number (PN) injection to achieve accurate compensation for dynamic IGE. An M-D coefficient extraction scheme based on GA is also proposed to extract the required compensation coefficients of the foreground calibration, which avoids falling into local traps through MATLAB. The above calibration scheme has been verified in a prototype 12-bit 750 MS/s pipelined ADC. The measurement results show that the signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are increased from 49.9 dB/66.7 dB to 59.6 dB/77.5 dB with the proposed calibration at 25 °C. With the help of background calibration at 85 °C, the SNDR and SFDR are improved by 3.4 dB and 8.8 dB, respectively.

A Bandwidth-Adaptive Pipelined SAR ADC With Three-Stage Cascoded Floating Inverter Amplifier

This article presents a bandwidth-adaptive pipelined successive approximation register (SAR) analog-to-digital converter (ADC) with a cascoded floating inverter amplifier (FIA). The proposed amplifier embeds a high-gain three-stage FIA in the closed-loop operation, realizing an accurate interstage gain. It features dynamically scaled bandwidth, thereby offering fast settling, good stability, high energy efficiency, and low noise simultaneously. Its fully dynamic operation enables bandwidth and event rate adaptiveness. Fabricated in 40-nm CMOS technology, the prototype ADC achieves an SNDR of 75.7 dB at 40 MS/s while consuming only 821 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu$</tex-math> </inline-formula> W, resulting in a Walden figure-of-merit (FoM) of 4.1 fJ/conversion step. It attains a nearly consistent performance and scalable power over 100 times the sampling rate variation.

Homogeneity Enforced Calibration of Stage Nonidealities for Pipelined ADCs

Pipelined analog-to-digital converters (ADCs) are fundamental components of various signal processing systems requiring high sampling rates and a high linearity. Over the past years, calibration techniques have been intensively investigated to increase the linearity. In this brief, we propose an equalization-based calibration technique which does not require knowledge of the ADC input signal for calibration. For that, a test signal and a scaled version of it are fed into the ADC sequentially, while only the corresponding output samples are used for calibration. Several test signal sources are possible, such as a signal generator (SG) or the system application (SA) itself. For the latter case, the presented method corresponds to a background calibration technique. Thus, slowly changing errors are tracked and calibrated continuously. Because of the low computational complexity of the calibration technique, it is suitable for an on-chip implementation. Ultimately, this brief contains an analysis of the stability and convergence behavior as well as simulation results.

A 16-Bit 120 MS/s Pipelined ADC Using a Multi-Level Dither Technique

In wireless applications, such as radars, tens of MHz signals need to be quantized using an analog-to-digital converter (ADC) with a large dynamic range. The detected signal amplitude can be random, with a small or large amplitude. In addition, the dynamic performance is degraded by capacitor mismatches. A 16-bit 120 MS/s pipelined ADC implemented in a 180 nm complementary metal–oxide–semiconductor (CMOS) process is presented in this work. We propose a multi-level dither technique that can significantly enhance the ADC linearity. The injected dither also helps improve the linearity when the ADC handles an input signal with a small amplitude. Traditional dither injection leads to an increase in the amplifier output swing. A counteracting dither injection scheme, both in sub-flash ADC and the multiplying digital-to-analog converter (MDAC), is proposed to remedy this issue. Moreover, capacitor mismatches in the first three pipeline stages are calibrated in a foreground way. The inter-stage residue gain accuracy is guaranteed by a gain-boosting amplifier. To demonstrate the effectiveness of the dither scheme, we obtained the dynamic performance of the ADC with a small input signal (−12 dBFS). The proposed calibration and dither injection technique improved the spurious-free dynamic range (SFDR) from 77 dBc to 85 dBc with −12 dBFS input. With −1 dBFS input, the SFDR remained at over 85 dBc, reaching up to the Nyquist input frequency. Therefore, the dither scheme enhances the dynamic performance when the ADC handles a signal with small amplitude.

A 12-bit 1.25 GS/s RF sampling pipelined ADC using a bandwidth-expanded residue amplifier with bias-free gain-boost technique

This paper describes a 12-bit 1.25-GS/s RF sampling pipelined analog-to-digital converter (ADC) implemented in a 28-nm CMOS process. To achieve high-speed and high-resolution conversion, a two-stage push-pull residue amplifier powered by a dual-supply is employed. A left half-plane (LHP) zero is generated through the coupling capacitance to expand the bandwidth and an inverter-based auxiliary amplifier is used to improve the gain and simplify the design. In addition, the proposed residue amplifier achieves a stable closed-loop characteristic without adding compensation capacitance, which greatly saves the area and improves the power efficiency. With an 18 MHz and 2 Vpp input signal, the SNDR is 61.5 dB, the SFDR is 70.2 dB. And the SNDR and SFDR are greater than 58 dB and 69 dB over the entire Nyquist bandwidth while the power consumption is 45.6 mW.

Dynamical analysis of a new chaotic system and its application in ADC

The improvement of Analog-to-Digital Converter (ADC) performance is crucial to improve the data quality of the signal acquisition system. Therefore, based on the dithering technology, combined with the chaotic system, the study designs and analyses a novel method to improve the Spurious-Free dynamic range (SFDR) of the ADC. First, a new five-dimensional chaotic system is proposed in this paper. The chaotic characteristics and dynamic behavior of the new system have been deeply analysed. The analysis methods mainly consist of the Lyapunov exponent, bifurcation diagram, power spectrum and sample entropy. The corresponding simulation model has been developed in Simulink, and the simulation results prove the reality and feasibility of the new chaotic system. Second, the random number homogenization universal algorithm is used to modify the amplitude of the chaotic sequences generated by the new chaotic system. The uniformity and correlation analysis prove that the Dither signal has strong uniformity and randomness. Third, a behaviour-level simulation model of the pipeline ADC is built; then, the narrowband, broadband and different amplitude Dither signals are added to verify the improvement effect for the dynamic performance of the ADC. The experimental results demonstrate that the designed method can improve the SFDR of the ADC by 10.37 dBc, which effectively eliminates the harmonic energy and improves the dynamic performance of the ADC.

A Self-Calibration Method of a Pipeline ADC Based on Dynamic Capacitance Allotment

This manuscript introduces a low-power mixed-signal foreground calibration algorithm of a pipeline analog-to-digital converter (ADC) using a digitally controlled reconfigurable switched-capacitor multiplying digital-to-analog converter (MDAC) gain controller. The proposed calibration technique forces the front-end stage MDAC gain toward its ideal value to achieve the ideal ADC output linearity. In this brief, a feedback mechanism has been employed to nullify the effect of change in MDAC gain from its ideal value by sensing a digital back-end unit response. The proposed method has been simulated using a 0.18-<inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS process. An 11-bit pipeline ADC with a 1.5-bit stage followed by a ten bit linear back-end ADC (BE-ADC) has been used to calibrate the non-linearity of the said 1.5-bit stage. Using a low amplifier gain value of 28 dB, the signal-to-noise-and-distortion ratio (SNDR) of the ADC improves from 46.21-dB pre-calibration to 65.13-dB post-calibration.

A digital background calibration technique for interstage gain nonlinearity in pipelined ADCs

This paper presents a digital background technique that intentionally exploits multiple dithers to calibrate conversion errors caused by interstage gain error and nonlinearity in high speed pipelined analog-to-digital converters (ADCs). Two independent, zero-mean pseudo-random signals are injected into the multiplying digital-to-analog converter (MDAC) alternately to estimate these errors. Least mean square (LMS) algorithms are adopted to quickly locate and track the calibration parameters. Simulation results are presented for a 800 MSps 12-bit pipelined ADC in a 40nm CMOS technology, similar to that described by Murmann and Boser [1], Keane et al. [2] and Nan Sun [3] using low-gain amplifiers. With calibration, the signal-to-noise-distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are improved from 32.74dB and 43.61dB to 70.54dB and 89.8dB, respectively. The proposed calibration technique has the advantages of simple implementation, arbitrary amplitude pseudo-random signals, and no restriction on the input signal of the ADC.