Reconfigurable Successive Approximation Register ADC and SAR-Assisted Pipeline ADC

Abstract

The paper proposes an analog to digital converter (ADC) which is reconfigurable and it consists of successive approximation register (SAR) ADC and SAR-Assisted pipeline ADC that can improve the resolution and conversion time based on the application. This reconfigurable ADC is designed to obtain an 8-bit resolution with low conversion time, a 16-bit (8-bit + 8-bit) resolution in pipeline mode with optimum conversion time and 16-bit (8-bit + 8-bit) resolution in sub ranging mode with more conversion time using exsisting components. This proposed ADC behaves as 8-bit SAR ADC, 16-bit (8-bit + 8-bit) two stage SAR-Assisted pipeline ADC and 16-bit (8-bit + 8-bit) two step sub-ranging ADC. The reconfigurability is obtained using control signals. This circuit has been designed and simulated in NI Multisim 14.0, and the results are presented in the paper.