A 12bit 1.6 GS/s pipelined ADC with multi-level dither injection achieving 68 dB SFDR over PVT

Abstract

This paper presents a 12-bit 1.6 GS/s pipelined analog-to-digital converter (ADC) in a 40-nm CMOS process. A novel dual-capacitor dither injection technique was proposed, based on a randomize multi-level uniform logic, aimed at leveraging multi-level signal jitter to disperse higher-order harmonics and spurious signals within the spectrum. The technique proves highly effective in preserving the linearity of high-speed pipeline ADCs under Process, Voltage, and Temperature (PVT) variations. Additionally, a high-speed amplifier with SC net was designed, and its matching bias circuit design can achieve configurable performance adjustment according to circumstances. Measurement results show that the ADC attains an impressive Signal-to-Noise and Distortion Ratio (SNDR) of 55.9 dB and Spurious-Free Dynamic Range (SFDR) of 71.7 dB at the Nyquist frequency. Furthermore, the SFDR variation remains below 4.2 dB over the temperature range of −40 °C–85 °C.