A low power 16-bit 50 MS/s pipeline ADC with 104 dB SFDR in 0.18 μm CMOS

Abstract

This paper presents a low-power 16-bit 50-MS/s pipeline analog-to-digital converter (ADC). An improved switched-capacitor bias technique is proposed to reduce power consumption while maintaining excellent performance, and a novel bootstrapped switch is implemented to improve the linearity further. An INL-(integral nonlinearity) based capacitor mismatch calibration is proposed to calibrate the capacitor match accuracy to the 16-bit level. The pipeline ADC is fabricated in a 0.18 μm mixed-signal CMOS process and the core size is 1.8 mm2. The implemented ADC is measured at a 50 MHz sampling rate under 1.8 V supply. After foreground calibration for capacitor mismatch errors, it achieves beyond 100 dB spur-free dynamic range (SFDR) and 75.3 dB signal-to-noise ratio (SNR). At the same time, the power consumption is 70.2 mW with 0.29 pJ/conv-step FOM (Figures-of-Merit).