Pipelined Analog-to-digital Converter Research Articles

Enhanced input range dynamic comparator for pipeline analogue-to-digital converter

A new dynamic comparator with enhanced input range is reported. Input trip point deviations from ideal values are shown to be less than a conventional comparator over a wide input range. This new dynamic comparator can be beneficial to low supply voltage analogue-to-digital converters (ADCs), especially to pipeline ADCs.

A 94-mW, 100-MS/s, 12-bit pipeline ADC for multi-standard TV demodulation applications

This paper presents the design and implementation of a 12-bit Analog-to-Digital Converter (ADC) for multi-standard TV demodulation applications. The ADC was fabricated in a standard digital 90-nm C...

A 16-bit cascaded sigma-delta pipeline A/D converter

A low-noise cascaded multi-bit sigma-delta pipeline analog-to-digital converter (ADC) with a low over-sampling rate is presented. The architecture is composed of a 2-order 5-bit sigma-delta modulator and a cascaded 4-stage 12-bit pipelined ADC, and operates at a low 8X oversampling rate. The static and dynamic performances of the whole ADC can be improved by using dynamic element matching technique. The ADC operates at a 4 MHz clock rate and dissipates 300 mW at a 5 V/3 V analog/digital power supply. It is developed in a 0.35 μm CMOS process and achieves an SNR of 82 dB.

Modeling, Quantitative Analysis, and Design of Switched-Current Pipeline A/D Converters

Switched-current (SI) analog-to-digital converters (ADCs) are desirable for biomedical applications. Until now, SI ADCs are lacking effective and systematic computer-aided analysis and design (CAD) tools, particularly for noise. In this paper, models for different SI multiplying-digital-to-analog-converter (MDAC) designs are analytically derived, with the inclusion of distortion and noise. The models can be further programmed into an equation-based SI analog CAD tool. In this paper, the equation-based models (EBMs) are used to quantitatively analyze SI MDACs. Simulation results show that noise significantly limit the performance of SI MDACs. Optimal performance boundaries are derived for single-ended and fully differential SI MDACs. The boundaries from EBMs are consistent with the published SI circuit measurements. A methodology is formulated to design efficient SI MDACs. The EBM and the design methodology are further verified by designs of two sample SI MDACs in an AMS 0.35-mum CMOS process with SPICE simulation. Results from the EBM match those from real circuit models well, except for the noise of SI MDACs with feedback, in which case, the design margin should be added to the target performance. For low-/medium-resolution (<12 bit) applications, a pipeline ADC with a simple SI MDAC is the most efficient. Nonetheless, single-ended SI ADCs are susceptible to source noise. For high-resolution applications, only fully differential SI pipeline ADCs can be selected.

A new structure of substage in pipelined analog-to-digital converters

The article presents a new (1+1)-bit/stage structure for pipelined analog-to-digital converters (ADC). When the input analog signal of the structure exceeds the converting range of the whole ADC, the signal can still be converted precisely and the output residue voltage of the structure will be in the converting range of the ADC. The structure is used in a 12-bit 40 MS/s pipelined ADC to test its function. The testing results show that the structure has right function and can correct the transition error induced by offset of comparators' decision levels. The ADC implemented in Semiconductor Manufactory International Corporation (SMIC) 0.18 μm CMOS process consumes 210 mW and occupies a chip area of 3.2×3.7 mm 2.

Single-Reference Foreground Calibration of High-Resolution, High-Speed Pipeline ADCs

The paper presents a digital foreground calibration technique for pipeline analog-to-digital converters (ADCs). While the conventional calibration approach requires additional buffered voltage references, the proposed technique requires only a voltage reference, already available in the converter, thus allowing a significant circuit simplification and silicon area savings. Since the number of buffered voltage references in the conventional calibration algorithm increases exponentially with the resolution of the conversion stages to be calibrated, the proposed technique is suitable for high-resolution, high-speed pipeline ADCs.

High speed, low power 100 MS/s front end track-and-hold amplifier for ten-bit pipelined ADC

The work focuses on the design of a high speed, low power track-and-hold amplifier (THA) for ten-bit 100 MS/s pipelined analogue-to-digital converter (ADC). A wide bandwidth and high gain two-stage operational transconductance amplifier (OTA) is selected as OTA of THA. This OTA consumes less amount of power and produce less thermal noise. The bootstrap technique is employed to reduce the non-linearity error associated with the input signal. The signal swing of the circuit is allowed to exceed the supply voltage (1.8 V), which further reduces the thermal noise contributed by the circuit and increases the dynamic range (DR) of the circuit. The circuit is implemented in UMC 180 nm digital CMOS technology. The THA circuit along with the biasing circuit consumes 5.706 mW power and it achieves 81.23 dB as the spurious free dynamic range (SFDR) for 2 V output at 100 MHz sampling rate. The dynamic range of the THA is 85.94 dB. The proposed THA is simulated using SPECTRE simulator under a variety of process and temperature conditions.

Principles of new method of optimisation, design and modelling of pipeline A/D converters

The paper presents the foundations of a new approach to design, optimisation and modelling of a new class of pipeline analogue-to-digital converters (PADC). The approach employs the results of analytical and applied research on the concurrent optimisation of the analogue and digital parts of adaptive estimation systems. Application of the approach allows to modify the known architecture and principles of conversion used in conventional PADC in the way significantly improving quality of conversion. Particularities of functioning of new PADC were studied in advanced simulation experiments, which confirmed the results of analytical investigations. Special attention was paid to comparison of the performance of new and known PADC and assessment of potentially achievable benefits.

Digital Background Calibration in Pipelined ADCs Using Commutated Feedback Capacitor Switching

We propose a new digital background calibration method for capacitor mismatches in pipelined analog-to-digital converters (ADCs). It combines commutated feedback capacitor switching with a background digital correlation loop to extract capacitor mismatch information, which is subsequently used to correct errors caused by the mismatch. This is an all-digital technique requiring minimal extra digital circuits, and is applicable to both single-bit and multibit-per-stage architectures. Simulations with a 15-stage, 1.5-bit-per-stage pipelined ADC with capacitor mismatch of sigma = 0.25% in each stage show that the technique improves signal-to-noise-distortion ratio from 62 dB (10 bits) to 94 dB (15.4 bits).

Calibration of sampling clock skew in SHA-less pipeline ADCs

A gradient-based algorithm to adaptively calibrate sampling clock skew in sample-and-hold amplifier (SHA)-less pipeline analogue-to-digital converters (ADCs) is presented. It follows that the power consumption of pipeline ADCs can be substantially reduced at the architecture level by employing the SHA-less multi-bit-per-stage architecture and remedying the resulting sampling clock skew problem with calibration.

New swapping technique for background calibration of capacitor mismatch and amplifier finite DC-gain in pipeline ADCs

A novel swapping technique for stage non-linear error calibration in Pipeline ADCs (analogue-to-digital converters) is presented in this paper. The proposed algorithm obtains an estimation of the mismatch between sampling capacitors in the MDAC (multiplying digital-to-analogue converter) inside each stage, without the necessity of interrupting the ADC operation, and therefore, suitable for background calibration applications. The technique also shows its applicability for the amplifier finite DC-gain error, providing a low-cost solution for full calibration of the main static errors in the Pipeline topology with less convergence time, memory resources and simpler calibration hardware than other existing calibration methods. In addition, this work overcomes practical limitations of previous adaptive approaches based on capacitor swapping by introducing a novel modulation scheme. This new scheme minimizes the impact on the analogue part and employs a very simple digital modulation logic.

An 8-bit 200-MSample/s Pipelined ADC With Mixed-Mode Front-End S/H Circuit

This paper describes an 8-bit pipelined analog-to-digital converter (ADC) using a mixed-mode sample-and-hold (S/H) circuit at the front-end. The mixed-mode sampling technique reduces signal swings in pipelined ADCs while maintaining the signal-to-noise ratio. The reduction of signal swings relaxes the operational amplifier (opamp) gain, slew rate, bandwidth, and capacitor-matching requirements in pipelined ADCs. Due to the mixed-mode S/H technique, the single-stage opamps and small capacitor sizes can be used in this pipelined ADC, leading to a high speed and low-power consumption. Fabricated in a 0.18-mum CMOS process, the 8-bit pipelined ADC consumes 22 mW with 1.8-V supply voltage. When sampling at 200 MSample/s, the prototype ADC achieves 54-dB spurious free dynamic range and 45-dB signal-to-noise and distortion ratio. The measured integral nonlinearity and differential nonlinearity are 0.34 LSB and 0.3 LSB, respectively.

A 0.5-V 8-bit 10-Ms/s Pipelined ADC in 90-nm CMOS

This paper presents a pipelined analog-to-digital converter (ADC) operating from a 0.5-V supply voltage. The ADC uses true low-voltage design techniques that do not require any on-chip supply or clock voltage boosting. The switch OFF leakage in the sampling circuit is suppressed using a cascaded sampling technique. A front-end signal-path sample-and-hold amplifier (SHA) is avoided by using a coarse auxiliary sample and hold (S/H) for the sub-ADC and by synchronizing the sub-ADC and pipeline-stage sampling circuit. A 0.5-V operational transconductance amplifier (OTA) is presented that provides inter-stage amplification with an 8-bit performance for the pipelined ADC operating at 10 Ms/s. The chip was fabricated on a standard 90 nm CMOS technology and measures 1.2 mm times 1.2 mm. The prototype chip has eight identical stages and stage scaling was not used. It consumes 2.4 mW for 10-Ms/s operation. Measured peak SNDR is 48.1 dB and peak SFDR is 57.2 dB for a full-scale sinusoidal input. Maximal integral nonlinearity and differential nonlinearity are 1.19 and 0.55 LSB, respectively.

A low power and low signal 4 bit 50MS/s double sampling pipelined ADC for Monolithic Active Pixel Sensors

A 4 bit very low power and low incoming signal analog todigital converter (ADC) using a double sampling switched capacitortechnique, designed for use in CMOS monolithic active pixels sensorreadout, has been implemented in 0.35μm CMOS technology. Anon-resetting sample and hold stage is integrated to amplify theincoming signal by 4. This first stage compensates both the amplifieroffset effect and the input common mode voltage fluctuations. Theconverter is composed of a 2.5 bit pipeline stage followed by a 2 bitflash stage. This prototype consists of 4 ADC double-channels; eachone is sampling at 50MS/s and dissipates only 2.6mW at 3.3V supplyvoltage. A bias pulsing stage is integrated in the circuit. Therefore,the analog part is switched OFF or ON in less than 1μs. The sizefor the layout is 80μm*0.9mm. This corresponds to the pitch of 4 pixelcolumns, each one is 20μm wide.

A Performance Model for the Design of Pipelined ADCs with Consideration of Overdrive Voltage and Slewing

This paper proposes a performance model for design of pipelined analog-to-digital converters (ADCs). This model includes the effect of overdrive voltage on the transistor, slewing of the operational amplifier, multi-bit structure of multiplying digital to analog converter (MDAC) and technology scaling. The conversion frequency of ADC is improved by choosing the optimum overdrive voltage of the transistor, an important consideration at smaller design rules. Moreover, multi-bit MDACs are faster than the single-bit MDACs when slewing occurs during the step response. The performance model of pipelined ADC shown in this paper is attractive for the optimization of the ADC's performances.

Digital Domain Measurement and Cancellation of Residue Amplifier Nonlinearity in Pipelined ADCs

Digital correction and calibration techniques have been extensively used to cancel linear circuit imperfections in pipelined analog-to-digital converters (ADCs). The self-calibration technique proposed in this paper provides a means of measuring and canceling nonlinear errors of interstage amplifiers in the digital domain. The calibration of nonlinearity coefficients is based on pseudorandom signal modulation and evaluation of digital code histograms. The scheme does not introduce additional precision hardware or test signals and operates in the background without interrupting normal converter operation. The simulation results of a 12-bit ADC show that the calibration is capable of improving the effective number of bits from 7 to 11.8 while achieving parameter adaptation time constants on the order of 100 ms at a sampling rate of 100 MS/s.

A 10-bit 60-MS/s Low-Power CMOS Pipelined Analog-to-Digital Converter

A 10-bit 60-MS/s low-power CMOS pipelined analog-to-digital converter (ADC) is proposed. At the front-end, a timing-skew-insensitive double-sampled Miller-capacitance-based sample-and-hold circuit is employed to enhance the dynamic performance of the pipelined ADC. Bootstrapped switch achieves rail-to-rail signal swing at low-voltage power supply. Employing double sampling and bias current scaling techniques, very competitive power consumption can be achieved. The prototype chips have been fabricated and experimental results confirm the feasibility of this new technique.

A Robust and Fast Digital Background Calibration Technique for Pipelined ADCs

This paper presents a background calibration scheme for pipelined analog-to-digital converters (ADCs) that is robust and has short calibration time. For a switched-capacitor (SC) pipeline stage, by splitting its input sampling capacitor, a random sequence can be injected into the ADC's signal path, and then calibration data can be extracted from the ADC's digital output without interrupting its normal conversion operation. Using an input-dependent scheme to generate the calibration random sequence, no additional signal range is required to accommodate the extra calibration signal. Furthermore, using random choppers to scramble signal can ensure that all necessary calibration data can be collected within a given time regardless of input conditions, resulting in a more robust ADC. A split-channel ADC architecture is proposed to reduce the calibration time. The split-channel ADC consists of two A/D channels that receive the same analog input but employ different random sequences for calibration. The calibration time can be greatly reduced by comparing the digital outputs from both channels and then removing the embedded perturbations before extracting the calibration data. The proposed calibration techniques are analyzed by using both theoretical formulation and system-level simulation.

Design Challenges of Analog-to-Digital Converters in Nanoscale CMOS

This paper discusses issues in the design of analog-to-digital converters (ADCs) in nanoscale CMOS and introduces some experimental designs incorporating techniques to solve these issues. Technology scaling increases the maximum conversion rate, but it decreases the gain and the SNR. To maintain a high SNR level despite the low-voltage operation, the power consumption needs to be increased. Because of lowered supply voltages, the design of circuits based on operational amplifiers (OpAmps) has become more difficult. Designs without OpAmps have therefore received more attention. One way of realizing low-voltage pipeline ADCs is by using comparator-controlled current sources, instead of conventional OpAmps. Furthermore, successive approximation ADCs and sub-ranging ADCs do not require OpAmps and are therefore suitable for low-voltage operation. ADC designers are now searching for suitable architectures for future nanoscale CMOS processes.

A 13-b Linear, 40-MS/s Pipelined ADC With Self-Configured Capacitor Matching

Using statistical matching properties of capacitor arrays, a pipelined ADC self-configures the multiplying digital-to-analog converter (MDAC) capacitor array for best matching from many trial combinations of smaller capacitive sub-elements. These sub-elements having opposite error magnitudes are grouped together to form matched elements thus permitting an accurate multi-bit MDAC to be created without using an explicit trimming network. A random search algorithm enables the self-configuration process by quickly regrouping the sub-elements to reduce the spread between the reconstructed elements. The proposed state machine based permutation algorithm allows near unique permutations of the sub-elements and achieves a near unity state repetition ratio with a simple hardware implementation. An analog-to-digital converter (ADC) system is designed with the self-configuration algorithm contained in the same die, and improvement in capacitor matching is demonstrated after the self-configuration process. A 0.18-mum CMOS prototype achieves 13-b linearity and over 80-dB spurious-free dynamic range (SFDR) at 43 MS/s. The chip consumes 268 mW at 1.8 V and occupies 3.6 mm2.