Pipelined Analog-to-digital Converter Research Articles

Oversampled pipeline A/D converters with mismatch shaping

This paper presents a pipeline analog-to-digital converter (ADC) with improved linearity. The linearity improvement is achieved through a combination of oversampling and mismatch shaping, which modulates the distortion energy out of band. Mismatch shaping can be realized in a traditional 1-bit/stage pipeline ADC, but the ADCs transfer characteristic properties limit its effectiveness at pushing the distortion out of band. These limitations can be alleviated by using a 1-bit/stage commutative feedback capacitor switching pipeline design. A test chip was fabricated in a 0.35-/spl mu/m CMOS process to demonstrate mismatch shaping. Experimental results obtained indicate that the spurious-free dynamic range improves by 8.5 dB to 76 dB when mismatch shaping is used at an oversampling ratio of 4 and a sampling rate of 61 MHz. The signal-to-noise and distortion ratio improves by 3 dB and the maximum integral nonlinearity decreases from 1.8 to 0.6 LSB at the 12-bit level.

An 8-b 100-MSample/s CMOS pipelined folding ADC

Although cascading reduces the number of folders used in folding analog-to-digital converters (ADCs), it demands wider bandwidth. The pipelining scheme proposed in this work greatly alleviates the wide bandwidth requirement of the folding amplifier. The pipelining is implemented with simple differential-pair folders. The key idea is to use odd multiples of folders with distributed interstage track/holds cooperatively with an algorithm for coding and digital error correction for the nonbinary system. The pipelined folding ADC prototyped using 0.5-/spl mu/m CMOS exhibits a differential nonlinearity (DNL) of /spl plusmn/0.4 LSB and an integral nonlinearity (INL) of /spl plusmn/1.3 LSB at 100 MSample/s. The chip occupies 1.4 mm/spl times/1.2 mm in active area and consumes 165 mW at 5 V.

A 3.3-V 12-b 50-MS/s A/D converter in 0.6-/spl mu/m CMOS with over 80-dB SFDR

A 12-b analog-to-digital converter (ADC) is optimized for spurious-free dynamic range (SFDR) performance at low supply voltage and suitable for use in modern wireless base stations. The 6-7-b two-stage pipeline ADC uses a bootstrap circuit to linearize the sampling switch of an on-chip sample-and-hold (S/H) and achieves over 80-dB SFDR for signal frequencies up to 75 MHz at 50 MSample/s (MSPS) without trimming, calibration, or dithering. INL is 1.3 LSB, differential nonlinearity (DNL) is 0.8 LSB. The 6-b and 7-b flash sub-ADCs are implemented efficiently using offset averaging and analog folding. In 0.6-/spl mu/m CMOS, the 16-mm/sup 2/ ADC dissipates 850 mW.

Digital cancellation of D/A converter noise in pipelined A/D converters

Pipelined analog-to-digital converters (ADCs) tend to be sensitive to component mismatches in their internal digital-to-analog converters (DACs), The component mismatches give rise to error, referred to as DAC noise, which is not attenuated or cancelled along the pipeline as are other types of noise. This paper describes an all-digital technique that significantly mitigates this problem. The technique continuously measures and cancels the portion of the ADC error arising from DAC noise during normal operation of the ADC, so no special calibration signal or auto-calibration phase is required. The details of the technique are described in the context of a nominal 14-bit pipelined ADC example at both the signal processing and register transfer levels. Through this example, the paper demonstrates that in the presence of realistic component matching limitations the technique can improve the overall ADC accuracy by several bits with only moderate digital hardware complexity.

Power optimization for pipeline analog-to-digital converters

Power optimization for pipeline analog-to-digital converters (ADCs) is presented. Pipeline ADCs with identical stages, parallel multiplying digital-to-analog converters (MDACs), capacitor scaling and resolution scaling are considered. Given the ratio R between the power consumption by each MDAC and that by each comparator in the sub-ADCs, the optimum bit resolution/stage and the corresponding minimum total power consumption are derived for each architecture. ADCs with capacitor scaling always achieve the lowest minimum power consumption. For ADCs with identical stages with a typical power ratio R of 10 to 20, the optimum number of bits/stage should be three or even four. These results serve as useful guidelines for designers in choosing the optimum number of bits/stage to minimize the ADC's power consumption.

A 10 b 50 MHz 320 mW CMOS A/D converter for video applications

This paper describes a 10b 50 MHz CMOS analog-to-digital converter (ADC) for high-speed signal processing applications. The proposed pipelined ADC adopts a selective channel-length adjustment technique for current mismatch minimization, a switched bias technique for power reduction of high-speed op amps, and a capacitor scaling technique for reduced power and chip area. The measured differential and integral nonlinearities of the prototype in a 0.8 /spl mu/m CMOS show less than /spl plusmn/0.6 LSB and /spl plusmn/2.0 LSB, respectively. The typical power consumption is 119 mW at 3 V and 40 MHz, and 320 mW at 5 V and 50 MHz.

A 13-b 10-Msample/s ADC digitally calibrated with oversampling delta-sigma converter

Two key techniques necessary to digitally calibrate multistep or pipelined converters are demonstrated in a differential 5-V, 13-b, 10-Msample/s analog-to-digital converter (ADC). One technique, called code-error calibration, is to linearize the transfer characteristic of digital-to-analog converters (DAC's) while the other, called gain-error proration, is to evenly distribute interstage gain errors over the full conversion range. The core of the former technique is an oversampling delta-sigma ratio calibrator working synchronously with the converter. This digital calibration process constantly tracks and updates the code errors without interfering with the normal operation. The prototype converter fabricated using a 1.4-/spl mu/m BiCMOS process consumes 360 mW with a 5-V single supply and exhibits a signal-to-noise ratio of 71 dB and a maximum end-point integral nonlinearity of 1.8 LSB at a 13-b level. The proposed techniques can be incorporated into general multistep or pipelined ADC's without sacrificing the conversion speed. >

An 8-b 85-MS/s parallel pipeline A/D converter in 1- mu m CMOS

A new architecture consisting of a time-interleaved array of pipelined analog-to-digital converters (ADCs) is presented. A prototype has been designed consisting of four switched-capacitor (S/C) multistage pipelined ADCs in parallel. Hardware cost is minimized by sharing resistor strings, bias circuitry and clock generation circuitry over the array. Digital error correction is employed to ease comparator accuracy requirements. Techniques are employed to minimize the effect of mismatches across the array. A key circuit issue is the design of a high-speed sample-and-hold (S/H) amplifier: a fully differential, mostly NMOS, non-folded-cascode operational-amplifier topology is used. An experimental chip was implemented in 1- mu m CMOS and 8-b resolution at a sample rate of 85 megasamples per second (MS/s) was obtained. Signal-to-noise plus distortion (S/(N+D)) was 41 dB for an input sinusoid of 40 MHz. >

A 15-b 1-Msample/s digitally self-calibrated pipeline ADC

A 15-b 1-Msample/s digitally self-calibrated pipeline analog-to-digital converter (ADC) is presented. A radix 1.93, 1 b per stage design is employed. The digital self-calibration accounts for capacitor mismatch, comparator offset, charge injection, finite op-amp gain, and capacitor nonlinearity contributing to DNL. A THD of -90 dB was measured with a 9.8756-kHz sine-wave input. The DNL was measured to be within +or-0.25 LSB at 15 b, and the INL was measured to be within +or-1.25 LSB at 15 b. The die area is 9.3 mm*8.3 mm and operates on +or-4-V power supply with 1.8-W power dissipation. The ADC is fabricated in an 11-V, 4-GHz, 2.4- mu m BiCMOS process.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Stress-sensitive properties of silicon-gate MOS devices : Hiroaki Mikoshiba. Solid-St. Electron.24, 221 (1981)

This paper introduces a digital background calibration technique for pipelined analog-to-digital converters (ADCs). The proposed method continuously measures and digitally corrects conversion errors resulting from residue amplifier gain error and nonlinearity. It is based on modulation of the residue voltage using a pseudorandom-noise sequence (PN). A least-mean-squares (LMS) algorithm is utilized to correct conversion errors arising from the residue amplifier non-idealities. Besides, a new statistics-based digitized residue distance estimation (DRDE) algorithm is proposed that allows the LMS algorithm to operate in the background without interrupting the normal operation of the ADC. The DRDE method extracts the residue amplifier non-idealities by evaluating the digitized residue voltage probability density function (PDF). Behavioral simulation results verify the usefulness of the proposed calibration technique and show that the signal-to-noise-and-distortion-ratio (SNDR) is improved from 43 to 71.9 dB, in a 12-bit pipelined ADC.