Pipelined Analog-to-digital Converter Research Articles

A calibration technique based on sub-stages’ weights of pipelined ADC

This paper describes an efficient background calibration technique for pipelined analog-to-digital converters (ADCs). This technique calibrate the interstage gain errors, capacitor mismatches and finite opamp open-loop gain by updating the weights of sub-stages that carry the information about these errors. A weight-based errors model is built to simplify calibration algorithm. The errors are merged into the weight of the corresponding stage. The first seven stages of every signal path are calibrated to achieve high resolution and eliminate errors. Two extra sub-stages are used in the calibration process to implement background calibration. The improved technique is used in a 14-bits 80 MS/s pipelined ADC. The results demonstrate that it can decrease errors, increase the effective number of bits by 2.04, and SFDR is 90.12 dB and ENOB is 13.2 bits. The ADC implemented in chartered 0.18 μm CMOS process consumes 260 mW, occupying a chip area of 7.16 mm2.

A 1-GS/s 9-bit Zero-Crossing-Based Pipeline ADC Using a Resistor as a Current Source

A zero-crossing-based circuit (ZCBC) is a promising technique for low-power high-resolution pipeline analog-to-digital converters (ADCs). Unfortunately, operating ZCBC ADCs at high speeds near 1 GS/s is quite challenging due to the delay of the zero-crossing detector that introduces nonlinear gain and offset errors. To solve nonlinearity, we propose a ZCBC pipeline ADC that employs a passive resistor as a current source. Due to its inherent linearity, the resistor-based ZCBC eliminates the input dependency of the interstage gain and offset errors, allowing a simple calibration. Furthermore, a background offset calibration scheme is proposed to cope with the large offset that results from high-speed operation. A prototype ADC implemented in 65-nm CMOS achieves an SNDR/SFDR of 47.26/62.64 dB at 1 GS/s while consuming 46.52 mW from 1 V supply.

A Power-Efficient Compact Pipelined ADC for ZigBee Receiver Applications

A pipelined analog-to-digital converter (ADC) that exhibits both power and area efficiencies is presented in this paper for ZigBee receiver applications. A combined opamp- and capacitor-sharing technique which presents a novel method to eliminate the memory effect is proposed. Fabricated in a 0.13-[Formula: see text]m CMOS process, the prototype 7-bit 16-MS/s ADC occupies 0.16[Formula: see text]mm2 active die area and achieves 41.9[Formula: see text]dB signal-to-noise-and-distortion ratio (SNDR), 52.1[Formula: see text]dB spurious-free dynamic rage (SFDR). The experimental results show that the figure of merit (FOM) is 1.12[Formula: see text]pJ/step and power dissipation is 1.82[Formula: see text]mW from a 1.2[Formula: see text]V supply.

A 1.1 V 10-bit 62MS/s pipeline ADC with two-step non-overlapping clock generation for multi I-Q channel RF receivers

A multi-channel pipeline analog-to-digital converter (ADC) with two-step non-overlapping clock generation is presented. Op-amp sharing and reference buffer sharing between channels are implemented ...

A background split algorithm for high speed pipelined ADCs

The non-ideal problem, include transfer function gain errors and timing offset between channels, seriously restrict pipelined analog-to-digital converters (ADCs) sampling rate upgrade. This letter analyzes these sources of errors and the effect they have on split architecture. Using Taylor approximation and the digital differentiator filter in a hybrid LMS algorithm, the new method does not need any additional analog circuitry, does not perturb the output samples, and does not require strictly well matched layout of signal path between two channels. Behavioral simulation results demonstrate that the proposed calibration technique can significantly improve signal-to-noise and distortion ratio and spurious free dynamic range performance from 63.8 to 79.8 dB and 65.7 to more than 90.0 dB, respectively, for a 13-bit 500 MS/s pipelined ADC.

Fully differential charge-pump comparator-based pipelined ADC in 90 nm CMOS

In this paper, a fully differential charge-pump comparator-based pipelined analog-to-digital converter (ADC) is presented. The fully differential capacitive gain doubler is used in the first stage as multiplying digital-to-analog converter (MDAC). Since the first stage cannot drive large capacitive loads, therefore a topology with high input impedance is chosen for the second, third and following stages. This topology does not require the common-mode feedback (CMFB) circuit. Besides, it employs the cascode current source to minimize the overshoot at the output of stages. The proposed ADC has been designed and simulated in a 90nm CMOS technology. Simulation results show that the ADC achieves SNDR of 55.6dB and SFDR of 64.5dB at sampling frequency of 100MS/s and consumes 2.8mW from a 1V power supply.

Analysis and Modeling of Imperfections in Multi-Bit Per Stage Pipelined ADCs

In this paper, an approach to estimate signal to noise ratio (SNR) and effective number of bits (ENOB) in nonideal multi-bit stages of pipelined analog to digital converters (ADCs) is presented. The most significant error sources in multistage ADCs are the capacitor mismatch and the finite and imprecise gain of amplifier. Output voltage of each stage in pipelined ADC is modeled by an ideal and a nonideal output, where nonideal output is the error due to circuit imperfections in each stage. Using an appropriate model, the SNR and ENOB due to circuit nonidealities and in terms of standard deviation of random errors are calculated. Simulation results show the accuracy of the analytical proposed approach in estimation of SNR and ENOB in multi-bit per stage pipelined converters.

A 1.1 V 10-bit 62MS/s pipeline ADC with two-step non-overlapping clock generation for multi I-Q channel RF receivers

A multi-channel pipeline analog-to-digital converter (ADC) with two-step non-overlapping clock generation is presented. Op-amp sharing and reference buffer sharing between channels are implemented without a front-end sample-and-hold amplifier for low power consumption. The proposed clock generator can easily implement short reset phases between non-overlapping clocks to remove the memory effect from opamp sharing. The prototype 4-channel ADCs are implemented in a 0.11 μm CMOS process. The 10 bit ADC achieve 56.6 dB (9.1 bit ENOB) SNDR and 72.2 dB SFDR with 3 MHz input frequency. Each ADC slice occupies 0.4 mm2 and consumes 13 mW at 62 MS/s sampling frequency under 1.1 V supply.

A SHA-less 14-bit, 100-MS/s pipelined ADC with comparator offset cancellation in background**Project supported by the National Natural Science Foundation of China (No. 61474092).

A 14-bit 100-MS/s pipelined analog-to-digital converter (ADC) without dedicated front-end sample-and-hold amplifier (SHA) is presented. In addition to elaborate matching of the sampling network in the first stage, a background offset cancellation circuit is proposed in this paper to suppress the offset of the comparators in the first-stage sub-ADC, which ensures the overall offset does not exceed the correction range of the built-in redundant structure. Fabricated in a 0.18-μm CMOS technology, the presented ADC occupies a chip area of 12 mm2, and consumes 237 mW from a 1.8-V power supply. Measurement results with a 30.1-MHz input sine wave under a sampling rate of 100 MS/s show that the ADC achieves a 71-dB signal-to-noise and distortion ratio (SNDR), an 85.4-dB spurious-free dynamic range (SFDR), a maximum differential nonlinearity (DNL) of 0.22 LSB and a maximum integral nonlinearity (INL) of 1.4 LSB.

Power and Area Efficient Pipelined ADC Stage in Digital CMOS Technology

ABSTRACTA power and area efficient metal-oxide semiconductor field-effect transistor (MOSFET)-only 1.5-bit fully differential pipelined analog-to-digital converter (ADC) stage is proposed and designed in TSMC 0.18 μm digital CMOS technology with supply voltage of 1.8 V. It is based on charge pump based technique to achieve the stage voltage gain of 2. Various capacitances are implemented by MOSCAPs (capacitance offered by the MOSFET), offering compatibility with cheaper digital complimentary metal-oxide semiconductor (CMOS) process in order to reduce the much required manufacturing cost. The proposed stage suffers from only linear gain error with full signal swing of 2 V peak-to-peak (p–p) differential. Using the proposed stage, un-calibrated signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) for 10-bit, 100 MS/s pipelined ADC are 40.11 and 40.86 dB, respectively, which can be further increased by using a simple digital calibration technique. Comparison between the proposed stage and conventional operational amplifier based stage shows insensitivity towards capacitor mismatch along with power savings and design simplicity.

Design and Power Optimization of High-Speed Pipelined ADC with Programmable Gain Amplifier for Wireless Receiver Applications

This paper proposes a 10-bit 100 MS/s 20 MHz low power pipelined analog-to-digital converter (ADC) with switched capacitor based programmable gain amplifier (PGA) suitable for wireless receiver applications. In the proposed ADC the double loading problem caused in the first stage of 10-bit pipelined ADC is avoided. In order to minimize the power consumption, split-capacitor sharing correlated double sampling and op-amp sharing technique has been used. Using the technique, low-gain operational amplifiers (op-amps) can be employed to implement a low-power pipelined ADC. Switched capacitor topology based PGA occupies an area of 0.0031 mm2. Switched capacitor topology based PGA with the integration of 10-bit pipelined ADC consumes 25.54 mW of power at 100 MS/s from a 1.8 V power supply.

Digital Calibration of DAC Unit Elements Mismatch in Pipelined ADCs

This paper presents a statistics-based digital background calibration technique for digital-to-analog converter (DAC) unit elements mismatch in pipelined analog-to-digital converters (ADCs). The proposed calibration method continuously measures and digitally mitigates sub-DAC (SDAC) mismatch errors in background during the normal data-conversion operation. In this method, the probability density function (PDF) of the sub-ADC (SADC) quantization error is analyzed using a two-level pseudorandom noise (PN) sequence in order to extract and remove SDAC mismatch errors. Behavioral simulation results are provided for a 12-bit pipelined ADC architecture to validate the effectiveness of the introduced method. Simulation results show that the signal-to-noise and distortion ratio (SNDR) is improved from 48.4 dB to 70.2 dB using the proposed calibration technique. This scheme converges after approximately $30\times 10^{6}$ clock cycles.

Digital Background Calibration of Residue Amplifier Non-idealities in Pipelined ADCs

In this paper, a digital background calibration technique for pipelined analog-to-digital converters (ADCs) is presented to continuously mitigate the conversion errors arising from the residue amplifier imperfections. The introduced method indirectly measures the digitized residue errors based on a novel principle. In the proposed method, the digitized residue errors are measured through the probability distribution of the digitized residue and a two-level pseudorandom noise sequence. Behavioral simulations are provided for a 12-bit pipelined ADC architecture to show the effectiveness of the proposed technique. The simulation results show that the signal-to-noise and distortion ratio is improved from 42.94 to 72.85 dB using the presented calibration technique. The required number of samples for convergence is approximately 5 $$\times $$× $$10^{6}$$106 clock cycles.

Exploiting Pipeline ADC Properties for a Reduced-Code Linearity Test Technique

Testing the static performances of high-resolution analog-to-digital converters (ADCs) consumes long test times that are disproportionately high with respect to the test time devoted to other types of circuits embedded in a modern system-on-chip (SoC). In this paper, we review the state-of-the-art of reduced-code linearity test methods for pipeline ADCs and we propose a new approach that increases the efficiency and accuracy of the method. We show that by exploiting some inherent properties in the architecture of pipeline ADCs we can achieve significant static test time reduction while maintaining the accuracy of the standard histogram test. The proposed method is demonstrated on a 55 nm 11-bit 2.5-bits/stage pipeline ADC.

A Predetermined LMS Digital Background Calibration Technique for Pipelined ADCs

A digital background calibration technique for pipelined analog-to-digital converters (ADCs) is proposed to correct the capacitor mismatch, finite dc gain, and nonlinearity of residue amplifiers. It divides the pipelined ADC into two equal channels and changes the decision points of sub-ADCs with a pseudorandom sequence to perform the digital background calibration. The difference between the digital outputs of the channels is used to drive the least mean square (LMS) machine to correct the mentioned errors and also the mismatch between the channels. In order to speed up the error correction, an accurate estimation for the errors is identified. The estimation is done by utilizing a piecewise linear model and a slope mismatch measurement technique in the digital domain. Behavioral simulations of a 12-bit 100-MS/s split pipelined ADC show that the convergence time of the proposed LMS calibration technique is significantly reduced in comparison with the conventional LMS algorithm for the same signal-to-noise-and-distortion ratio.

A Calibration Technique for Pipelined ADCs Using Self-Measurement and Histogram-Based Test Methods

This brief presents a digital background calibration technique for pipelined analog-to-digital converters (ADCs) to correct the capacitor mismatch, finite dc gain, and nonlinearity of residue amplifiers. It estimates the calibration coefficients at start-up by a modified self-measurement method with low-precision stimulation signals in the multistage calibration. Then, during the ADC normal operation, a sliding histogram in the vicinity of the decision boundaries of stage comparators is utilized to adjust the calibration coefficients in order to follow the variation of errors. To do so, the ratio of information achieved from the initial and new histograms is used to update the calibration coefficients. Behavioral simulation results of a 12-bit pipelined ADC show that the proposed calibration technique improves the ADC linearity by more than 4 bits and it is robust against the variation of errors.

An Integrator-Based Pipelined ADC With Digital Calibration

A 12-bit pipelined analog-to-digital converter (ADC) uses a first-stage integrator-based open-loop residue amplifier and integrator nonlinearities are foreground calibrated. In the remaining traditional closed-loop stages, gain errors and memory errors are background calibrated. Separate reference voltages are used in the first three ADC stages to reduce interstage coupling. A 0.25- $\mu\mbox{m}$ CMOS prototype dissipates 140 mW and occupies an active area of 5 mm 2. At 40 megasamples/s (40 MS/s) , the calibration improves the spurious-free dynamic range from 51.2 to 95.1 dB and the signal-to-noise-plus-distortion ratio from 43.7 to 69.0 dB.

A statistics-based digital background calibration technique for pipelined ADCs

This paper introduces a digital background calibration technique for pipelined analog-to-digital converters (ADCs). The proposed method continuously measures and digitally corrects conversion errors resulting from residue amplifier gain error and nonlinearity. It is based on modulation of the residue voltage using a pseudorandom-noise sequence (PN). A least-mean-squares (LMS) algorithm is utilized to correct conversion errors arising from the residue amplifier non-idealities. Besides, a new statistics-based digitized residue distance estimation (DRDE) algorithm is proposed that allows the LMS algorithm to operate in the background without interrupting the normal operation of the ADC. The DRDE method extracts the residue amplifier non-idealities by evaluating the digitized residue voltage probability density function (PDF). Behavioral simulation results verify the usefulness of the proposed calibration technique and show that the signal-to-noise-and-distortion-ratio (SNDR) is improved from 43 to 71.9dB, in a 12-bit pipelined ADC.

A 10-bit 120-MS/s pipelined ADC with improved switch and layout scaling strategy

A 10 bit, 120 MS/s two-channel pipelined analog-to digital converter (ADC) is presented. The ADC is featured with improved switch by using the body effect to improve its conduction performance. A scaling down strategy is proposed to get more efficiency in the OTAs layout design. Implemented in a 0.18-μm CMOS technology, the ADC's prototype occupied an area of 2.05 × 1.83 mm2. With a sampling rate of 120-MS/s and an input of 4.9 MHz, the ADC achieves a spurious-free-dynamic range of 74.32 dB and signal-to-noise-and-distortion ratio of 55.34 dB, while consuming 220-mW/channel at 3-V supply.

Design of a novel wideband op amp with CCII structure

A wideband op amp for high speed pipelined analog to digital converter (ADC) is presented. The main amplifier adopts cascode structure and the auxiliary amplifier employs CCII structure. A current-mode feedback circuit is utilized to stabilize the out common mode voltage through adjusting the currents of the main amplifier. Test results show that the circuit has an open loop gain of 83.19 dB, a unity gain bandwidth of 1.6 GHz. Compared with traditional amplifier, the present op amp possesses lower power dissipation and higher response speed. A pipelined ADC for high-resolution video signal process using this op amp achieves a resolution of 10 bits and a sampling rate of 170 MS/s.