A background split algorithm for high speed pipelined ADCs

Abstract

The non-ideal problem, include transfer function gain errors and timing offset between channels, seriously restrict pipelined analog-to-digital converters (ADCs) sampling rate upgrade. This letter analyzes these sources of errors and the effect they have on split architecture. Using Taylor approximation and the digital differentiator filter in a hybrid LMS algorithm, the new method does not need any additional analog circuitry, does not perturb the output samples, and does not require strictly well matched layout of signal path between two channels. Behavioral simulation results demonstrate that the proposed calibration technique can significantly improve signal-to-noise and distortion ratio and spurious free dynamic range performance from 63.8 to 79.8 dB and 65.7 to more than 90.0 dB, respectively, for a 13-bit 500 MS/s pipelined ADC.