Abstract
A digital background calibration technique based on the concept of split analog-to-digital converter (ADC) structure is proposed for pipelined ADCs to correct the gain error induced by the capacitors mismatch and finite dc gain of the residue amplifiers and nonlinearity of the residue amplifiers. In the proposed technique, one of the channels in split ADC structure is virtually implemented by using two extra comparators in each ADC’s stage and an interpolation filter to eliminate the mismatch between channels. Several circuit-level simulation results in the context of a 12-bit 100-MS/s pipelined ADC are provided to verify the usefulness of the proposed calibration technique. The simulation results show 51-dB signal-to-noise and distortion ratio and 65-dB spurious free dynamic range improvement, respectively, in comparison with the noncalibrated ADC.
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